pxa255_dmac.h

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// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header: pxa255_dmac.h
//
//  Defines the DMA controler register layout and associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_DMAC_H_
#define _PXA255_DMAC_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  DMAC_REG_T
//
//  Defines the DMAC control register layout.
//
//------------------------------------------------------------------------------

typedef struct 
{
	VUINT32_T	DDADR;  // descriptor address reg
	VUINT32_T	DSADR;  // source address register
	VUINT32_T	DTADR;  // target address register
	VUINT32_T	DCMD;   // command address register
} DMADescriptor_T;

typedef struct 
{
    VUINT32_T	DCSR[16];		//DMA CSRs by channel
    VUINT32_T	RSVD0[44];
    VUINT32_T	DINT;			//DMA interrupt Register
    VUINT32_T	RSVD1[3];
    VUINT32_T	DRCMR[40];
    VUINT32_T	RSVD2[24];
    DMADescriptor_T DDG[16];	// 16 channels of descriptor registers 
} DMAC_REG_T, *PDMAC_REG_T;

//
//  bit mask constants
//
#define DCMD_LENGTH(x)  	(x & 0x01FFF)
#define DCMD_WIDTH(x)   	((x & 0x3) << 14)
#define DCMD_SIZE(x)    	((x & 0x3) << 16)
#define DCMD_ENDIAN     	(0x1 << 18)
#define DCMD_ENDIRQEN   	(0x1 << 21)
#define DCMD_STARTIRQEN 	(0x1 << 22)
#define DCMD_FLOWTRG    	(0x1 << 28)
#define DCMD_FLOWSRC    	(0x1 << 29)
#define DCMD_INCTRGADDR 	(0x1 << 30)
#define DCMD_INCSRCADDR 	(0x1 << 31)

#define DCSR_BUSERRINTR     (0x1U << 0)  // Bus error status bit
#define DCSR_STARTINTR      (0x1U << 1)  // Descriptor fetch status 
#define DCSR_ENDINTR        (0x1U << 2)  // finish status
#define DCSR_STOPINTR       (0x1U << 3)  // stopped status
#define DCSR_REQPEND        (0x1U << 8)  // Request Pending (read-only)
#define DCSR_STARTIRQEN     (0x1U << 21) // Enable the start interrupt (when the descriptor is loaded)
#define DCSR_STOPIRQEN      (0x1U << 29) // Enable the stopped interrupt (when the descriptor is done)
#define DCSR_NOFETCH        (0x1U << 30) // Descriptor fetch mode, 0 = fetch
#define DCSR_RUN            (0x1U << 31) // run, 1=start

#define DDADR_STOPCONTINUE  (0x1U << 0)
#define DDADR_ADDRESS_MASK	0xFFFFFFF0
#define DMA_MAX_TRANSFER	8191

#define DRCMRx_MAPVLD		(0x1U << 7)	// Request channel indicated by DRCMRx(3:0)

#define DRCMR0_DREQ0		0			// DRCMR0  - map dma channel for DREQ0
#define DRCMR1_DREQ1		1			// DRCMR1  - map dma channel for DREQ1
#define DRCMR2_I2S_RX		2			// DRCMR2  - map dma channel for I2S RX
#define DRCMR3_I2S_TX		3			// DRCMR3  - map dma channel for I2S TX
#define DRCMR4_BTUART_RX	4			// DRCMR4  - map dma channel for BTUART RX
#define DRCMR5_BTUART_TX	5			// DRCMR5  - map dma channel for BTUART TX
#define DRCMR4_FFUART_RX	6			// DRCMR6  - map dma channel for FFUART RX
#define DRCMR5_FFUART_TX	7			// DRCMR7  - map dma channel for FFUART TX
#define DRCMR8_AC97_MIC		8			// DRCMR8  - map dma channel for AC97 microphone
#define DRCMR9_AC97_MDM_RX	9			// DRCMR9  - map dma channel for AC97 modem rx
#define DRCMR10_AC97_MDM_TX	10			// DRCMR10 - map dma channel for AC97 modem tx
#define DRCMR11_AC97_AUD_RX	11			// DRCMR11 - map dma channel for AC97 audio rx
#define DRCMR12_AC97_AUD_TX	12			// DRCMR12 - map dma channel for AC97 audio tx
#define DRCMR13_SSP_RX		13			// DRCMR13 - map dma channel for SSP RX
#define DRCMR14_SSP_TX		14			// DRCMR14 - map dma channel for SSP TX
#define DRCMR15_NSSP_RX		15			// DRCMR15 - map dma channel for NSSP RX
#define DRCMR16_NSSP_TX		16			// DRCMR16 - map dma channel for NSSP TX
#define DRCMR17_ICP_RX		17			// DRCMR17 - map dma channel for ICP RX
#define DRCMR18_ICP_TX		18			// DRCMR18 - map dma channel for ICP TX
#define DRCMR19_STUART_RX	19			// DRCMR19 - map dma channel for STUART RX
#define DRCMR20_STUART_TX	20			// DRCMR20 - map dma channel for STUART TX
#define DRCMR21_MMC_RX		21			// DRCMR21 - map dma channel for MMC RX
#define DRCMR22_MMC_TX		22			// DRCMR22 - map dma channel for MMC TX

#define DRCMR25_USBEP1		25			// DRCMR25 - map dma channel for USB EP 1
#define DRCMR26_USBEP2		26			// DRCMR26 - map dma channel for USB EP 2
#define DRCMR27_USBEP3		27			// DRCMR27 - map dma channel for USB EP 3
#define DRCMR28_USBEP4		28			// DRCMR28 - map dma channel for USB EP 4
#define DRCMR29_HWUART_RX	29			// DRCMR29 - map dma channel for HWUART RX
#define DRCMR30_USBEP6		30			// DRCMR30 - map dma channel for USB EP 6
#define DRCMR31_USBEP7		31			// DRCMR31 - map dma channel for USB EP 7
#define DRCMR32_USBEP8		32			// DRCMR32 - map dma channel for USB EP 8
#define DRCMR33_USBEP9		33			// DRCMR33 - map dma channel for USB EP 9
#define DRCMR34_HWUART_TX	34			// DRCMR34 - map dma channel for HWUART TX
#define DRCMR35_USBEP11		35			// DRCMR35 - map dma channel for USB EP 11
#define DRCMR36_USBEP12		36			// DRCMR36 - map dma channel for USB EP 12
#define DRCMR37_USBEP13		37			// DRCMR37 - map dma channel for USB EP 13
#define DRCMR38_USBEP14		38			// DRCMR38 - map dma channel for USB EP 14

//
// DMAC channels
//
typedef enum
{
	DMAC_CHANNEL_0 = 0,
	DMAC_CHANNEL_1,
	DMAC_CHANNEL_2,
	DMAC_CHANNEL_3,
	DMAC_CHANNEL_4,
	DMAC_CHANNEL_5,
	DMAC_CHANNEL_6,
	DMAC_CHANNEL_7,
	DMAC_CHANNEL_8,
	DMAC_CHANNEL_9,
	DMAC_CHANNEL_10,
	DMAC_CHANNEL_11,
	DMAC_CHANNEL_12,
	DMAC_CHANNEL_13,
	DMAC_CHANNEL_14,
	DMAC_CHANNEL_15
}DMAC_CHANNEL_T, *P_DMAC_CHANNEL_T;

#define INVALID_DMA_CHANNEL    0xFF

//------------------------------------------------------------------------------

#if __cplusplus
}
#endif

#endif