pxa255_uart.h

老外的一个开源项目

// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header:  pxa255_uart.h
//
//  Defines the UART controller register layout associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_UART_H_
#define _PXA255_UART_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  XXUART_REG_T
//
//  Defines the UART control register layout.
//
//------------------------------------------------------------------------------

//
//  UART control registers.
//
typedef struct {
	VUINT32_T	THR_RBR_DLL;// DLAB = 0  WO  8bit - Transmit Holding Register (THR).
							// DLAB = 0  RO  8bit - Receive Buffer Register (RBR).
							// DLAB = 1  RW  8bit - Divisor Latch Low Register (DLL).
	VUINT32_T	IER_DLH;	// DLAB = 0  RW  8bit - Interrupt Enable Register.
	VUINT32_T	IIR_FCR;	// DLAB = X  RO  8bit - Interrupt Identification Register.
	VUINT32_T	LCR;		// DLAB = X  RW  8bit - Line Control Register.
	VUINT32_T	MCR;		// DLAB = X  RW  8bit - Modem Control Regiser.
	VUINT32_T	LSR;		// DLAB = X  RO  8bit - Line Status Register.
	VUINT32_T	MSR;		// DLAB = X  RO  8bit - Modem Status Register.
	VUINT32_T	SCR;		// DLAB = X  RW  8bit - Scratchpad Register.
	VUINT32_T	ISR;		// DLAB = X  RW  8bit - IrDA Select Register.
} UART_REG_T, *PUART_REG_T;

//
// FFUART
//
typedef UART_REG_T	FFUART_REG_T;
typedef UART_REG_T	*PFFUART_REG_T;

//
// BTUART
//
typedef UART_REG_T	BTUART_REG_T;
typedef UART_REG_T	*PBTUART_REG_T;

//
// STUART
//
typedef UART_REG_T	STUART_REG_T;
typedef UART_REG_T	*PSTUART_REG_T;

//
// HWUART
//
typedef struct {
	VUINT32_T	THR_RBR_DLL;// DLAB = 0  WO  8bit - Transmit Holding Register (THR).
							// DLAB = 0  RO  8bit - Receive Buffer Register (RBR).
							// DLAB = 1  RW  8bit - Divisor Latch Low Register (DLL).
	VUINT32_T	IER_DLH;	// DLAB = 0  RW  8bit - Interrupt Enable Register.
	VUINT32_T	IIR_FCR;	// DLAB = X  RO  8bit - Interrupt Identification Register.
	VUINT32_T	LCR;		// DLAB = X  RW  8bit - Line Control Register.
	VUINT32_T	MCR;		// DLAB = X  RW  8bit - Modem Control Regiser.
	VUINT32_T	LSR;		// DLAB = X  RO  8bit - Line Status Register.
	VUINT32_T	MSR;		// DLAB = X  RO  8bit - Modem Status Register.
	VUINT32_T	SCR;		// DLAB = X  RW  8bit - Scratchpad Register.
	VUINT32_T	ISR;		// DLAB = X  RW  8bit - IrDA Select Register.
	VUINT32_T	ABR;		// DLAB = X  RW  8bit - Auto-Baud Control Register.
	VUINT32_T	ACR;		// DLAB = X  RW  8bit - Auto-Baud Count Register.
} HWUART_REG_T, *PHWUART_REG_T;


//
// line status register (LSR) bit definitions
//
#define UART_LSR_DR			0x00000001
#define UART_LSR_OE			0x00000002
#define UART_LSR_PE			0x00000004
#define UART_LSR_FE			0x00000008
#define UART_LSR_BI			0x00000010
#define UART_LSR_TDRQ		0x00000020
#define UART_LSR_TEMT		0x00000040
#define UART_LSR_FIFOE		0x00000080

#define	UART_LSR_ERRORS		(0x0000008E)

//
// modem control register (MCR) bit definitions
//
#define UART_MCR_DTR		0x00000001
#define UART_MCR_RTS		0x00000002
#define UART_MCR_OUT1		0x00000004
#define UART_MCR_OUT2		0x00000008
#define UART_MCR_LOOP		0x00000010
#define UART_MCR_AFE		0x00000020

//
// modem status register (MSR) bit definitions
//
#define UART_MSR_DCTS		0x00000001
#define UART_MSR_DDSR		0x00000002
#define UART_MSR_TERI		0x00000004
#define UART_MSR_DDCD		0x00000008
#define UART_MSR_CTS		0x00000010
#define UART_MSR_DSR		0x00000020
#define UART_MSR_RI			0x00000040
#define UART_MSR_DCD		0x00000080

//
// interrupt enable register (IER) bit definitions
//
#define UART_IER_RAVIE		0x00000001
#define UART_IER_TIE		0x00000002
#define UART_IER_RLSE		0x00000004
#define UART_IER_MIE		0x00000008
#define UART_IER_RTOIE		0x00000010
#define UART_IER_NRZE		0x00000020
#define UART_IER_UUE		0x00000040
#define UART_IER_DMAE		0x00000080

//
// interrupt identification register (IIR) bit definitions
//
#define UART_IIR_IP			0x00000001
#define UART_IIR_IID1		0x00000002
#define UART_IIR_IID2		0x00000004
#define UART_IIR_IID3		0x00000008

#define UART_IIR_FIFOES0	0x00000040
#define UART_IIR_FIFOES1	0x00000080

//
// FIFO control register (FCR) bit definitions
//
#define UART_FCR_TRFIFOE	0x00000001
#define UART_FCR_RESETRF	0x00000002
#define UART_FCR_RESETTF	0x00000004

#define UART_FCR_ITL0		0x00000040
#define UART_FCR_ITL1		0x00000080

//
// Irda selection register (ISR) bit definitions
//
#define UART_ISR_XMITIR		0x00000001
#define UART_ISR_RCVEIR		0x00000002
#define UART_ISR_XMODE		0x00000004
#define UART_ISR_TXPL		0x00000008
#define UART_ISR_RXPL		0x00000010

#define UART_FIFO_DEPTH		64


#define UART_DATA_LENGTH_5	0x00
#define UART_DATA_LENGTH_6	0x01
#define UART_DATA_LENGTH_7	0x02
#define UART_DATA_LENGTH_8	0x03



//------------------------------------------------------------------------------

#if __cplusplus
    }
#endif

#endif