pxa255.inc

老外的一个开源项目

;Copyright (c) David Vescovi.  All rights reserved.
;Part of Project DrumStix
;Windows Embedded Developers Interest Group (WE-DIG) community project.
;http://www.we-dig.org
;Copyright (c) Microsoft Corporation.  All rights reserved.
;------------------------------------------------------------------------------
;
;  File:  pxa255.inc
;
;  This include file defines only those registers bit fields required by the startup
;  code. All addresses are based off the physical addresses (PA) defined
;  in pxa255_base_reg.inc.
;
;------------------------------------------------------------------------------
	IF	!:DEF: _pxa255_inc_
_pxa255_inc_				EQU		1

	INCLUDE pxa255_base_regs.inc


;
; Reset Controller Status Register
;
RCSR_VALID_MASK			EQU		(0x0F)
RCSR_HARD_RESET			EQU		(0x1)
RCSR_WDOG_RESET			EQU		(0x1 << 1)
RCSR_SLEEP_RESET		EQU		(0x1 << 2)
RCSR_GPIO_RESET			EQU		(0x1 << 3)

;
; Power Manager Sleep Status Register
;
PSSR_VALID_MASK			EQU		(0x37)
PSSR_PH					EQU		(0x1 << 4)
PSSR_RDH				EQU		(0x1 << 5)

;
; Core Clock (frequency) Configuration Register
;
CCCR_VALID_MASK			EQU		(0x3FF)
CCCR_L27				EQU		(0x01)
CCCR_M1					EQU		(0x1 << 5)
CCCR_M2					EQU		(0x2 << 5)
CCCR_M4					EQU		(0x3 << 5)
CCCR_N10				EQU		(0x2 << 7)		; N=1.0
CCCR_N15				EQU		(0x3 << 7)		; N=1.5
CCCR_N20				EQU		(0x4 << 7)		; N=2.0
CCCR_N25				EQU		(0x5 << 7)		; N=2.5
CCCR_N30				EQU		(0x6 << 7)		; N=3.0

;
; CCLKCFG (cp14:6)
;
CCLKCFG_TURBO			EQU		(0x1)
CCLKCFG_FCS				EQU		(0x1 << 1)

;
; Clock Enable Register
;
CKEN_VALID_MASK			EQU		(0x17BFF)

;
; Power Manager Control Register
;
PMCR_IDAE				EQU		(0x1)

;
; Power Manager General Configuration Register
;
PCFR_OPDE				EQU		(0x1)
PCFR_FP					EQU		(0x1 << 1)
PCFR_FS					EQU		(0x1 << 2)
PCFR_DS					EQU		(0x1 << 3)

;
; Power Manager Wake-Up Enable Register
;
PWER_WE0				EQU		(0x1)
PWER_WE1				EQU		(0x1 << 1)
PWER_WE2				EQU		(0x1 << 2)
PWER_WE3				EQU		(0x1 << 3)
PWER_WE4				EQU		(0x1 << 4)
PWER_WE5				EQU		(0x1 << 5)
PWER_WE6				EQU		(0x1 << 6)
PWER_WE7				EQU		(0x1 << 7)
PWER_WE8				EQU		(0x1 << 8)
PWER_WE9				EQU		(0x1 << 9)
PWER_WE10				EQU		(0x1 << 10)
PWER_WE11				EQU		(0x1 << 11)
PWER_WE12				EQU		(0x1 << 12)
PWER_WE13				EQU		(0x1 << 13)
PWER_WE14				EQU		(0x1 << 14)
PWER_WE15				EQU		(0x1 << 15)
PWER_WERTC				EQU		(0x1 << 31)

;
; Oscillator Configuration Register
;
OSCC_OOK				EQU		(0x1)
OSCC_OON				EQU		(0x1 << 1)

;
; SDRAM MDCNFG Register
;
MDCNFG_DE0				EQU		(0x1)
MDCNFG_DE1				EQU		(0x1 << 1)
MDCNFG_DWID0			EQU		(0x1 << 2)
MDCNFG_DCAC0			EQU		(0x3 << 3)
MDCNFG_DRAC0			EQU		(0x3 << 5)
MDCNFG_DNB0				EQU		(0x1 << 7)
MDCNFG_DTC0				EQU		(0x3 << 8)
MDCNFG_DADDR0			EQU		(0x1 << 10)
MDCNFG_DLATCH0			EQU		(0x1 << 11)
MDCNFG_DSA1111_0		EQU		(0xF << 12)
MDCNFG_DE2				EQU		(0x1 << 16)
MDCNFG_DE3				EQU		(0x1 << 17)
MDCNFG_DWID2			EQU		(0x1 << 18)
MDCNFG_DCAC2			EQU		(0x3 << 19)
MDCNFG_DRAC2			EQU		(0x3 << 21)
MDCNFG_DNB2				EQU		(0x1 << 23)
MDCNFG_DTC2				EQU		(0x3 << 24)
MDCNFG_DADDR2			EQU		(0x1 << 26)
MDCNFG_DLATCH2			EQU		(0x1 << 27)
MDCNFG_DSA1111_2		EQU		(0xF << 28)

;
; SDRAM MDREFR Register
;
MDREFR_VALID_MASK		EQU		(0x03DFFFFF)
MDREFR_DRI				EQU		(0xFFF)
MDREFR_E0PIN			EQU		(0x1 << 12)
MDREFR_K0RUN			EQU		(0x1 << 13)
MDREFR_K0DB2			EQU		(0x1 << 14)
MDREFR_E1PIN			EQU		(0x1 << 15)
MDREFR_K1RUN			EQU		(0x1 << 16)
MDREFR_K1DB2			EQU		(0x1 << 17)
MDREFR_K2RUN			EQU		(0x1 << 18)
MDREFR_K2DB2			EQU		(0x1 << 19)
MDREFR_APD				EQU		(0x1 << 20)
MDREFR_SLFRSH			EQU		(0x1 << 22)
MDREFR_K0FREE			EQU		(0x1 << 23)
MDREFR_K1FREE			EQU		(0x1 << 24)
MDREFR_K2FREE			EQU		(0x1 << 25)


; Current Program Status Register
; Processor mode
CPSR_Mode_MASK			EQU		(0x0000001F)
CPSR_Mode_USR			EQU		(0x10)
CPSR_Mode_FIQ			EQU		(0x11)
CPSR_Mode_IRQ			EQU		(0x12)
CPSR_Mode_SVC			EQU		(0x13)
CPSR_Mode_ABT			EQU		(0x17)
CPSR_Mode_UND			EQU		(0x1B)
CPSR_Mode_SYS			EQU		(0x1F)
; Interrupt masks
CPSR_FBit				EQU		(0x40)
CPSR_IBit				EQU		(0x80)
CPSR_DeIrqFiq			EQU		(0xC0)
CPSR_EnIrqFiq			EQU		(0xFFFFFF3F)

    ENDIF ; !:DEF: _pxa255_inc_
    END