pxa255_lcd.h

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// Copyright (c) David Vescovi.  All rights reserved.
// Part of Project DrumStix
// Windows Embedded Developers Interest Group (WE-DIG) community project.
// http://www.we-dig.org
// Copyright (c) Microsoft Corporation.  All rights reserved.
//------------------------------------------------------------------------------
//
//  Header: pxa255_lcd.h
//
//  Defines the LCD controler register layout and associated types and constants.
//
//------------------------------------------------------------------------------
#ifndef _PXA255_LCD_H_
#define _PXA255_LCD_H_

#if __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
//
//  Type:  LCD_REG_T
//
//  Defines the LCD controler register layout.
//
//------------------------------------------------------------------------------

typedef struct
{
	VUINT32_T	LCCR0;			// 0x4400 0000
	VUINT32_T	LCCR1;			// 0x4400 0004
	VUINT32_T	LCCR2;			// 0x4400 0008
	VUINT32_T	LCCR3;          // 0x4400 000C
	VUINT32_T	reserved0[4];   // 0x4400 0010
	VUINT32_T	FBR0;           // 0x4400 0020
	VUINT32_T	FBR1;           // 0x4400 0024
	VUINT32_T	reserved1[4];   // 0x4400 0028
	VUINT32_T	LCSR;           // 0x4400 0038
	VUINT32_T	LIIDR;          // 0x4400 003C
	VUINT32_T	TRGBR;          // 0x4400 0040
	VUINT32_T	TCR;            // 0x4400 0044
	VUINT32_T	reserved2[110]; // 0x4400 0048
	VUINT32_T	FDADR0;         // 0x4400 0200
	VUINT32_T	FSADR0;         // 0x4400 0204
	VUINT32_T	FIDR0;          // 0x4400 0208
	VUINT32_T	LDCMD0;         // 0x4400 020C
	VUINT32_T	FDADR1;         // 0x4400 0210
	VUINT32_T	FSADR1;         // 0x4400 0214
	VUINT32_T	FIDR1;          // 0x4400 0218
	VUINT32_T	LDCMD1;         // 0x4400 021C
} LCD_REG_T, *PLCD_REG_T;


typedef struct 
{
	UINT16	palette[256];
}LCD_PALETTE_T;


typedef struct  
{
    UINT32	FDADR;     // Pointer to next frame descriptor (Physical address)
    UINT32	FSADR;     // Pointer to the data (Physical address)
    UINT32	FIDR;      // Frame descriptor ID
    UINT32	LDCMD;     // DMA command
    UINT32	PHYSADDR;  // PHYSADDR contains the physical address of this descriptor.
}LCD_FRAME_DESCRIPTOR_T;


//
// LCD Controller Control Register 0 (LCCR0)
//
#define LCD_ENB		0x00000001
#define LCD_CMS		0x00000002
#define LCD_SDS		0x00000004
#define LCD_LDM		0x00000008
#define LCD_SFM		0x00000010
#define LCD_IUM		0x00000020
#define LCD_EFM		0x00000040
#define LCD_PAS		0x00000080
#define LCD_BLE		0x00000100
#define LCD_DPD		0x00000200
#define LCD_DIS		0x00000400
#define LCD_QDM		0x00000800
#define LCD_PDD(n)	((n) << 12)
#define LCD_BM		0x00100000
#define LCD_OUM		0x00200000

//
// LCD Controller Control Register 1 (LCCR1)
//
#define LCD_PPL(n)	((n))
#define LCD_HSW(n)	((n) << 10)
#define LCD_ELW(n)	((n) << 16)
#define LCD_BLW(n)	((n) << 24)

//
// LCD Controller Control Register 2 (LCCR2)
//
#define LCD_LPP(n)	((n))
#define LCD_VSW(n)	((n) << 10)
#define LCD_EFW(n)	((n) << 16)
#define LCD_BFW(n)	((n) << 24)

//
// LCD Controller Control Register 3 (LCCR3)
//
#define LCD_PCD(n)	((n))
#define LCD_ACB(n)	((n) << 8)
#define LCD_API(n)	((n) << 16)
#define LCD_VSP		0x00100000
#define LCD_HSP		0x00200000
#define LCD_PCP		0x00400000
#define LCD_OEP		0x00800000
#define LCD_BPP(n)	((n) << 24)
#define LCD_DPC		0x08000000

//
// LCD Controller DMA Frame Descriptor Address Registers (FDADRx)
//
#define LCD_FDADR(n)	((n) & 0xFFFFFFF0)

//
// LCD Controller DMA Frame Source Address Registers (FSADRx)
//
#define LCD_FSADR(n)	((n) & 0xFFFFFFF8)

//
// LCD Controller DMA Frame ID Registers (FIDRx)
//
#define LCD_FIDR(n)		((n) & 0xFFFFFFF8)

//
// LCD Controller DMA Command Registers (LDCMDx)
//
#define LCD_Len(n)		((n))
#define LCD_EOFInt		0x00200000
#define LCD_SOFInt		0x00400000
#define LCD_Pal			0x04000000

//
// LCD Controller DMA Frame Branch Registers (FBRx)
//
#define LCD_BRA			0x00000001
#define LCD_BINT		0x00000002
#define LCD_SrcAddr(n)	((n) << 4)

//
// LCD Controller Status Register (LCSR)
//
#define LCD_LDD		0x00000001
#define LCD_SOF		0x00000002
#define LCD_BER		0x00000004
#define LCD_ABC		0x00000008
#define LCD_IUL		0x00000010
#define LCD_IUU		0x00000020
#define LCD_OU		0x00000040
#define LCD_QD		0x00000080
#define LCD_EOF		0x00000100
#define LCD_BS		0x00000200
#define LCD_SINT	0x00000400

//
// LCD Controller TMED RGB Seed Register (TRGBR)
//
#define LCD_TRS(n) ((n))
#define LCD_TGS(n) ((n) << 8)
#define LCD_TBS(n) ((n) << 16)


//
// LCD Controller TMED Control Register (TCR)
//
#define LCD_TM2S	0x00000001
#define LCD_TM1S	0x00000002
#define LCD_TM2En	0x00000004
#define LCD_TM1En	0x00000008
#define LCD_TVBS(n)	((n) << 4)
#define LCD_THBS(n)	((n) << 8)
#define LCD_TSCS(n)	((n) << 12)
#define LCD_TED		0x00004000

//------------------------------------------------------------------------------

#if __cplusplus
}
#endif

#endif