startup.s

老外的一个开源项目

;++
; Copyright (c) David Vescovi.  All rights reserved.
; Part of Project DrumStix
; Windows Embedded Developers Interest Group (WE-DIG) community project.
; http://www.we-dig.org
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Abstract:
;
;    This module implements PXA255 initialization code.
;    It's responsible for setting up the chips core.
;
;
;--

	OPT   2					; disable listing
	INCLUDE kxarm.h
	INCLUDE pxa255.inc
	INCLUDE pxa255_macros.inc
	INCLUDE gumstix.inc

	OPT   1					; reenable listing

	IMPORT	OALStartUp
	EXPORT	FreqChange 



;************************************************************************
;   StartUp() is the entry point on Reset (all forms of Reset)
;
;   Desription:  StartUp is the first routine executed when powering on
;       the system.  It is also executed first after all forms of XScale
;       resets.
;
;       Regardless of the build type, we disable the MMU and caches
;       immediately and flush'em.
;
;       This routine includes all of the necessary core-level
;       initialization code to get the chip up.
;       Most other initialization takes place in the bootloaders Main
;       function.
;
;       The MMU assumed to be inactive at this time so physical addresses
;       should be used.
;
;
;************************************************************************

	STARTUPTEXT
	LEAF_ENTRY StartUp

; Interrupt and exception vectors
	B		Reset_Handler
	B		Undefined_Handler
	B		SWI_Handler
	B		Prefetch_Handler
	B		Abort_Handler
	NOP									; Reserved Vector
	B		IRQ_Handler
	B		FIQ_Handler

; **********************************
Undefined_Handler
	b		Undefined_Handler
; **********************************

SWI_Handler
    b		SWI_Handler
; **********************************

Prefetch_Handler
	b		Prefetch_Handler
; **********************************

Abort_Handler
	b		Abort_Handler
; **********************************

IRQ_Handler
	b		IRQ_Handler
; **********************************

FIQ_Handler
	b		FIQ_Handler
; **********************************




; ********************************************************************
;  Entry Point on RESET
Reset_Handler

	; Put the CPU in Supervisor mode (SVC) and disable IRQ and FIQ interrupts.
	ldr		r0, =(CPSR_Mode_SVC :OR: CPSR_DeIrqFiq)
	msr		cpsr_c, r0

	; disable MMU, instruction and data chaches, and the write buffer
	ldr		r0, =0x2001					; enable access to all coprocessors
	mcr		p15, 0, r0, c15, c1, 0
	CPWAIT	r0

    ldr		r0, =0x00000078				; turn things off (must write bits[6:3] as 1s)
    mcr		p15, 0, r0, c1, c0, 0		; turn off MMU, I&D caches, and write buffer 
    CPWAIT	r0

	ldr		r0, =0x00000000			
	mcr		p15, 0, r0, c8, c7, 0		; flush instruction and data tlb
	mcr		p15, 0, r0, c7, c7, 0		; flush instruction and data caches
	mcr		p15, 0, r0, c7, c10, 4		; drain the write buffer
	nop
	nop
	nop

	mvn		r0, #0						; grant manager access to all domains
	mcr		p15, 0, r0, c3, c0, 0
   
	ldr		r0, =0x80000000				; lowest RAM address
	cmp		pc, r0						; if we are already in RAM (debugging)
	bhi		%30							; don't init the memory controler

	; Init MEMC
	ldr		r12, =PXA255_BASE_REG_PA_CLK
	ldr		r0, =(CCCR_L27 :OR: CCCR_M1 :OR: CCCR_N10) ;default
	str		r0, [r12, #CCCR_OFFSET]
	ldr		r0, =0x00000000				; all clocks off for now
	str		r0, [r12, #CKEN_OFFSET]
	ldr		r0, =0x00000000
	str		r0, [r12, #OSCC_OFFSET]
	mov		r1, #CCLKCFG_FCS
	mcr		p14, 0, r1, c6, c0, 0

	; allow internal clocks to settle by waiting for a little bit
	ldr		r2, =OSCR					; get OS Timer Count
	ldr		r3, [r2]
	; now wait a full 200usec
	add		r3, r3, #0x300				; really 0x2E1 about 200usec, so 0x300
10
	ldr		r4, [r2]
	cmp		r4, r3
	bmi		%B10

	; write msc0, read back to ensure data latches
	; get memory controller base address
	ldr		r1, =PXA255_BASE_REG_PA_MEMC
	ldr		r2, =MSC0_INROM_value		; Slow FLASH access while in ROM

	; Caution: Don't rewrite flash timing values while executing out of flash.
	; two seperate initialization values. one for when we are in RAM one for
	; ROM (Flash) .. ROM is default loaded above.
	ldr		r0, =0x80000000
	cmp		pc, r0
	blo		MSC0_end					; rom ..jump over
	; rewrite register if RAM version
	ldr		r2, =MSC0_INRAM_value

MSC0_end
	str		r2, [r1, #MSC0_OFFSET]
	ldr		r2, [r1, #MSC0_OFFSET]
	; write msc1
	ldr		r2, =MSC1_value
	str		r2, [r1, #MSC1_OFFSET]
	ldr		r2, [r1, #MSC1_OFFSET]
	; write msc2
	ldr		r2, =MSC2_value
	str		r2, [r1, #MSC2_OFFSET]
	ldr		r2, [r1, #MSC2_OFFSET]

	; Step 1b: Write MECR, MCMEM0, MCMEM1, MCATT0,
	;               MCATT1, MCIO0, MCIO1 (Skip on gumstix)
	; Step 1c: Write MDREFR:K0RUN and MDREFR:E0PIN Configure MDREFR:K0DB2.
	;          Retain the current values of MDREFR:APD and MDREFR:SLFRSH.
	;          MDREFR:DRI must contain a valid value.
	;          Deassert MDREFR:KxFREE. (Skip on gumstix)

	ldr		r3, =MDREFR
	ldr		r2, [r3]					; read MDREFR value
	str		r2, [r3]					; configure K2DB1 and K2DB2

	ldr		r0, =0xfff
	bic		r2, r2, r0					; Clear DRI -- INTEL TOOL LEAVES THIS STEP OUT!!
	orr		r2, r2, #0x018				; configure a valid SDRAM Refresh Interval (DRI)
	str		r2, [r3]

	; Step 2: Configure Synchronous Static memory (Skip on gumstix)

	; Step 4: In systems that have SDRAM, transition SDRAM through the following states:
	;         a. self-refresh
	;         b. power-down
	;         c. PWRDNX
	;         d. NOP */

	orr		r2, r2, #MDREFR_K1RUN		; assert K1RUN for SDCLK1
	str		r2, [r3]					; self-refresh and clock-stop -> self-refresh
	bic		r2, r2, #MDREFR_SLFRSH		; clear SLFRSH bit field
	str		r2, [r3]					; self-refresh -> Power-down
	orr		r2, r2, #MDREFR_E1PIN		; set the E1PIN bit field
	str		r2, [r3]					; Power-down -> PWRDNX
	nop									; no action required from PWRDNX -> NOP

	; Step 4f: Write MDCNFG (with enable bits deasserted), MDCNFG:DE3:2,1:0 set to 0.

	ldr		r3, =MDCNFG					; Load SDRAM Config register.
	;														 Must not enable yet.
	ldr		r2, =MDCNFG_value			; Value from Intel tool
	str		r2, [r3]					; Write to MDCNFG register

	; Step 5: For systems with SDRAM, wait specified NOP power-up waiting period
	; required by SDRAMs to ensure SDRAMs receive a stable clock with a NOP condition.

	ldr		r2, =OSCR					; get OS Timer Count
	ldr		r3, [r2]
	; now wait a full 200usec
	add		r3, r3, #0x300				; really 0x2E1 about 200usec, so 0x300
20
	ldr		r4, [r2]
	cmp		r4, r3
	bmi		%B20

	; Step 6: Ensure data cache disabled -- should not be needed out of reset

	mov		r0, #0x78					; turn everything off
	mcr		p15, 0, r0, c1, c0, 0		; caches off, MMU off, etc.

	CPWAIT	r0

	;   Step 7: On hardware reset systems that contain SDRAM, trigger specified number (typically
	;	eight) of refresh cycles by attempting non-burst read or write accesses to any disabled
	;	SDRAM bank. Each such access causes a simultaneous CBR refresh cycles for all four banks,
	;	which causes a pass through the CBR state and back to NOP. On the first pass, the PALL state
	;	occurs before the CBR state.

	;  Access memory *not yet enabled* for CBR refresh cycles (8)
	;  - CBR is generated for all banks
	ldr		r2, =0xA0000000
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]
	str		r2, [r2]

	; Step 8: Can re-enable DCACHE if it was disabled above (Skip)

	; Step 9: Enable SDRAM partitions

	ldr		r3, [r1, #MDCNFG_OFFSET]
	orr		r3, r3, #(MDCNFG_DE0 :OR: MDCNFG_DE1_value)	; enable partition(s)
	str		r3, [r1, #MDCNFG_OFFSET]

	; Step 10: In systems with SDRAM, write MDMRS register to trigger MRS command to all
	; enabled banks of SDRAM. For each SDRAM partition pair that has one or both partitions
	; enabled, this forces a pass through the MRS state and back to NOP. The CAS latency 
	; must be the only variable option and is derived from the value programmed in the
	; MDCNFG:MDTC0,2 fields. Burst type programmed to sequential and the length is set
	; to four.

	ldr		r2, =MDMRS_value			; the writable bits will be written as a 0
	str		r2, [r1, #MDMRS_OFFSET]

	; Step 11: (optional) Enable auto-power-down

	ldr		r3, [r1, #MDREFR_OFFSET]
	orr		r3, r3, #MDREFR_APD			; set the APD bit
	str		r3, [r1, #MDREFR_OFFSET]	; write to MDREFR

30
	b		OALStartUp

;-------------------------------------------------------------------------------

	LTORG
    
;-------------------------------------------------------------------------------
;
; FreqChange: Frequence change sequence.
;
; Inputs:
; 
; On return:
;
; Register used: r1
;
;-------------------------------------------------------------------------------
;
	ALIGN
FreqChange
	mov		r1, #2						; frequency change bit
	mcr		p14, 0, r1, c6, c0, 0		; write CCLKCFG
;	ldr		r2, =MDREFR					; reset the refresh timer
;	ldr		r1, [r2]
;	str		r1, [r2]					; re-write the value
	
	mov		pc, lr

;-------------------------------------------------------------------------------

    LTORG

;-------------------------------------------------------------------------------
;

    END