📄 uda1341ts.c.svn-base
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#include "config.h"
#include "lib.h"
#ifdef _DEBUG
#include <stdio.h>
#endif /* _DEBUG */
#define L3CLOCK (0x10) /*(1<<4) GPB4 = L3CLOCK*/
#define L3DATA (0x8) /*(1<<3) GPB3 = L3DATA */
#define L3MODE (0x4) /*(1<<2) GPB2 = L3MODE */
#define GPB2_OUTPUT (0x1 << 4) /* set output */
#define GPB3_OUTPUT (0x1 << 6)
#define GPB4_OUTPUT (0x1 << 8)
#define GPE0_I2SLRCK (0x2 << 0)
#define GPE1_I2SSCLK (0x2 << 2)
#define GPE2_CDCLK (0x2 << 4)
#define GPE3_I2SSDI (0x2 << 6)
#define GPE4_I2SSDO (0x2 << 8)
#define L3MODE_LOW() {GPBDAT &= ~(L3MODE);}
#define L3MODE_HIGH() {GPBDAT |= (L3MODE);}
#define L3DATA_LOW() {GPBDAT &= ~(L3DATA);}
#define L3DATA_HIGH() {GPBDAT |= (L3DATA);}
#define L3CLOCK_LOW() {GPBDAT &= ~(L3CLOCK);}
#define L3CLOCK_HIGH() {GPBDAT |= (L3CLOCK);}
#define UDA1341_ADDR ((1 << 2) + (1 << 4)) /*0x14*/
#define UDA1341_REG_DATA0 (0 << 0) /*0x0*/
#define UDA1341_REG_STATUS (2 << 0) /*0x2*/
#define UDA1341_EXT_ADDR ((1 << 7) + (1 << 6)) /*0xC0*/
#define VOLUME_MAX ((1 << 5) + (1 << 4) + (1 << 3) + (1 << 2) + (1 << 1) + (1 << 0)) /*0x3F*/
#define BASS_MAX ((1 << 3) + (1 << 2) + (1 << 1) + (0 << 0)) /*0xE*/
#define TREBLE_MAX ((1 << 1) + (1 << 0)) /*0x3*/
#define NO_RESET (0x0 << 6)
#define RESET (0x1 << 6)
#define _SC_256_FS
#ifdef _SC_256_FS
#define EXTCLK_FRE (0x2 << 4)
#define MASCLK_FRE (0x0 << 2)
#define SYSTEM_CLK 256
#else
#define EXTCLK_FRE (0x1 << 4)
#define MASCLK_FRE (0x1 << 2)
#define SYSTEM_CLK 384
#endif
#define IF_IIS (0x0 << 1)
#define IF_LSB_16 (0x1 << 1)
#define IF_LSB_18 (0x2 << 1)
#define IF_LSB_20 (0x3 << 1)
#define IF_MSB (0x4 << 1)
#define NO_DC_FLITERING (0x0 << 0)
#define DC_FLITERING (0x1 << 1)
#define TR_DMA_DISABLE (0x0 << 5)
#define TR_DMA_ENABLE (0x1 << 5)
#define RE_DMA_DISABLE (0x0 << 4)
#define RE_DMA_ENABLE (0x1 << 4)
#define TR_CHA_NO_IDLE (0x0 << 3)
#define TR_CHA_IDLE (0x1 << 3)
#define RE_CHA_NO_IDLE (0x0 << 2)
#define RE_CHA_IDLE (0x1 << 2)
#define IIS_PSR_DISABLE (0x0 << 1)
#define IIS_PSR_ENABLE (0x1 << 1)
#define IIS_INTFCE_ STOP (0x0 << 0)
#define IIS_INTFCE_START (0x0 << 0)
#define IIS_MASTER_MOD (0x0 << 8)
#define IIS_SLAVE_MOD (0x1 << 8)
#define IIS_NO_TR (0x0 << 6)
#define IIS_RE_MOD (0x1 << 6)
#define IIS_TR_MOD (0x2 << 6)
#define IIS_RE_TR_MOD (0x3 << 6)
#define IIS_LOW_LCHA (0x0 << 5)
#define IIS_HIGH_LCHA (0x1 << 5)
#define IIS_COMP_FORMAT (0x0 << 4)
#define MSB_JUST_FORMAT (0x1 << 4)
#define PER_CHA_8bit (0x0 << 3)
#define PER_CHA_16bit (0x1 << 3)
#define SBCLK_FRE_16fs (0x0 << 0)
#define SBCLK_FRE_32fs (0x1 << 0)
#define SBCLK_FRE_48fs (0x2 << 0)
#define TR_FIFO_NOR (0x0 << 15)
#define TR_FIFO_DMA (0x1 << 15)
#define RE_FIFO_NOR (0x0 << 14)
#define RE_FIFO_DMA (0x1 << 14)
#define TR_FIFO_DISABLE (0x0 << 13)
#define TR_FIFO_ENABLE (0x1 << 13)
#define RE_FIFO_DISABLE (0x0 << 12)
#define RE_FIFO_ENABLE (0x1 << 12)
static int g_volume = 80, g_bass = 0, g_treble = 0, g_mute = 0;
static
void L3_write_addr(unsigned char data)
{
int i,j;
L3MODE_LOW();
L3CLOCK_HIGH();
for(j=0;j<4;j++) /*L3 set up time > 190ns */
;
for(i=0;i<8;i++)
{
if(data&0x1)
{
L3CLOCK_LOW();
L3DATA_HIGH();
for(j=0;j<4;j++) /*L3 clock cycle time > 500ns */
;
L3CLOCK_HIGH();
L3DATA_HIGH();
for(j=0;j<4;j++)
;
}
else
{
L3CLOCK_LOW();
L3DATA_LOW();
for(j=0;j<4;j++)
;
L3CLOCK_HIGH();
L3DATA_LOW();
for(j=0;j<4;j++)
;
}
data >>= 1;
}
L3CLOCK_HIGH();
L3MODE_HIGH();
}
static
void L3_write_data(unsigned char data, int halt)
{
int i,j;
if(halt)
{
L3CLOCK_HIGH();
for(j=0;j<4;j++) /*tstp(L3) > 190ns */
;
}
L3CLOCK_HIGH();
L3MODE_HIGH();
for(j=0;j<4;j++) /*tsu(L3) > 190ns */
;
for(i=0;i<8;i++)
{
if(data & 0x1)
{
L3MODE_HIGH();
L3CLOCK_LOW();
L3DATA_HIGH();
for(j=0;j<4;j++)
;
L3MODE_HIGH();
L3CLOCK_HIGH();
L3DATA_HIGH();
for(j=0;j<4;j++)
;
}
else
{
L3MODE_HIGH();
L3CLOCK_LOW();
L3DATA_LOW();
for(j=0;j<4;j++)
;
L3MODE_HIGH();
L3CLOCK_HIGH();
L3DATA_LOW();
for(j=0;j<4;j++)
;
}
data >>= 1;
}
L3CLOCK_HIGH();
L3MODE_HIGH();
}
void set_volume(int val)
{
if(val < 0)
val = 0;
if(val > 100)
val = 100;
g_volume = val;
val = VOLUME_MAX - (val * VOLUME_MAX) / 100;
L3_write_addr( UDA1341_ADDR + UDA1341_REG_DATA0 );
L3_write_data(val, 0);
}
void set_bass(int val)
{
if(val < 0)
val = 0;
if(val > 100)
val = 100;
g_bass = val;
val = BASS_MAX - (val * BASS_MAX) / 100;
val = (1 << 6) + (val << 2) + (TREBLE_MAX - (g_treble * TREBLE_MAX) / 100);
L3_write_addr( UDA1341_ADDR + UDA1341_REG_DATA0 );
L3_write_data(val,0);
}
void set_treble(int val)
{
if(val < 0)
val = 0;
if(val > 100)
val = 100;
g_treble = val;
val = TREBLE_MAX - (val * TREBLE_MAX) / 100;
val = (1 << 6) + ((BASS_MAX - (g_bass * BASS_MAX) / 100) << 2) + val;
L3_write_addr( UDA1341_ADDR + UDA1341_REG_DATA0 );
L3_write_data(val, 0);
}
void set_mute(int val)
{
g_mute = (val != 0);
val = (1 << 7) + (1 << 5) + (0 << 3) + (val ? (1 << 2) : 0) + 0;
L3_write_addr( UDA1341_ADDR + UDA1341_REG_DATA0 );
L3_write_data(val, 0);
}
void init_uda1341ts(int mode)
{
/*
* L3MODE GPB2
* L3DATA GPB3
* L3CLOCK GPB4
*/
GPBCON &= (~0x3F0);
GPBCON |= (GPB4_OUTPUT | GPB3_OUTPUT | GPB2_OUTPUT);
GPBUP = GPBUP | 0x1c;
L3MODE_HIGH();
L3CLOCK_HIGH();
/* 0,1,10,000,0:reset,256fs,iis,no dcfilter */
L3_write_addr( UDA1341_ADDR + UDA1341_REG_STATUS );
L3_write_data( RESET + EXTCLK_FRE + IF_IIS + NO_DC_FLITERING, 0 );
/*0,0,10,000,0:no reset,256fs,iis,no dcfilter */
L3_write_addr( UDA1341_ADDR + UDA1341_REG_STATUS );
L3_write_data( NO_RESET + EXTCLK_FRE + IF_IIS + NO_DC_FLITERING, 0 );
/*1,0,0,0,0,0,01:OGS=0,IGS=0,ADC_non-inverting,DAC_non-inverting,single speed playback,ADCoffDACon */
L3_write_addr( UDA1341_ADDR + UDA1341_REG_STATUS );
L3_write_data((1 << 7) + (1 << 0), 0);
set_volume(g_volume);
set_bass(g_bass);
set_treble(g_treble);
set_mute(g_mute);
/*
* I2SLRCK GPE0
* I2SSCLK GPE1
* CDCLK GPE2
* I2SSDI GPE3
* I2SSDO GPE4
*/
GPECON &= (~0x3FF);
GPECON |= (GPE4_I2SSDO | GPE3_I2SSDI | GPE2_CDCLK | GPE1_I2SSCLK | GPE0_I2SLRCK);
GPEUP = GPEUP | 0x1f;
/*XXX - 根据mode修改相应的IISCON和IISFCON配置*/
/* Initialize the IIS bus */
/*Tx DMA disable,Rx DMA disable, Tx no idle, Rx idle, enable pre-divider*/
IISCON = TR_DMA_DISABLE | RE_DMA_DISABLE | TR_CHA_NO_IDLE | RE_CHA_IDLE | IIS_PSR_ENABLE;
/*Tx FIFO access normal,Tx FIFO enable*/
IISFCON = TR_FIFO_NOR | TR_FIFO_ENABLE;
/* XXX
* 1. 是不是所有的音频文件都可以用IIS data format播放或录音？
* 2. ======================是16位/声道？
* 3. ======================都采用256fs？
* 4. ======================都采用32fs？
*/
/*main mode, transmit mode,low,IIS data format,16 bit,256fs,32fs*/
IISMOD = IIS_MASTER_MOD | IIS_TR_MOD | IIS_LOW_LCHA | IIS_COMP_FORMAT | PER_CHA_16bit | MASCLK_FRE | SBCLK_FRE_32fs;
/*
* 1. 参考Linux中的代码，计算IISPSR
*/
/*IISPSR = (5<<5) | 5;XXX*/
/*IISPSR = (8 << 5) | 8;*/
if(mode) /*record*/
{
/*1,0,1,0,0,0,10 : OGS=0,IGS=1,ADC_NI,DAC_NI,sngl speed,AonDoff*/
L3_write_addr( UDA1341_ADDR + UDA1341_REG_STATUS ); /*STATUS (000101xx+10)*/
L3_write_data( (1 << 7) + (1 << 5) + (1 << 1) , 0 );
/*11000,010 : DATA0, Extended addr(010) */
L3_write_addr( UDA1341_ADDR + UDA1341_REG_DATA0 ); /*DATA0 (000101xx+00)*/
L3_write_data( UDA1341_EXT_ADDR + (2 << 0) , 0 );
/*010,011,01 : DATA0, MS=9dB, Ch1=on Ch2=off, */
L3_write_data( (2 << 5) + (3 << 2) + (1 << 0) , 0 );
/* Initialize the IIS bus */
/*Tx DMA disable,Rx DMA disable, Tx no idle, Rx idle, enable pre-divider*/
IISCON = TR_DMA_DISABLE | RE_DMA_DISABLE | TR_CHA_IDLE | RE_CHA_NO_IDLE | IIS_PSR_ENABLE;
/*Re FIFO access normal,Re FIFO enable*/
IISFCON = RE_FIFO_NOR | RE_FIFO_ENABLE;
/*main mode, transmit mode,low,IIS data format,16 bit,256fs,32fs*/
IISMOD = IIS_SLAVE_MOD | IIS_RE_MOD | IIS_LOW_LCHA | IIS_COMP_FORMAT | PER_CHA_16bit | MASCLK_FRE | SBCLK_FRE_32fs;;
}
}
void wav_play(struct WAVE *hdr, int *data)
{
int i, NumSamples,Psr_Divider;
#ifdef _DEBUG
printf("ChunkID=0x%08x\nFormat=0x%08x\nSubchunk1ID=0x%08x\nSubchunk2ID=0x%08x\n",
hdr->ChunkID, hdr->Format, hdr->Subchunk1ID, hdr->Subchunk2ID);
printf("NumChannels=%d\nSampleRate=%d\nBitsPerSample=%d\n",
hdr->NumChannels, hdr->SampleRate, hdr->BitsPerSample);
#endif
Psr_Divider = PCLK / ( SYSTEM_CLK * (hdr->SampleRate)) - 1;
IISPSR = (Psr_Divider << 5) | Psr_Divider;
IISCON |= 0x1;
NumSamples = hdr->Subchunk2Size/hdr->NumChannels/(hdr->BitsPerSample/8);
for(i = 0; i < NumSamples; i++)
{
while(IISCON & 0x80)
;
IISFIFO = *(data++);
}
}
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