📄 can_testbench.v
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send_bit(1); // INTER send_bit(1); // INTER#80; send_bit(0); // SOF send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID a send_bit(0); // ID send_bit(1); // ID send_bit(1); // ID send_bit(0); // ID 6 send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID send_bit(1); // RTR send_bit(1); // IDE send_bit(0); // ID 0 send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID 0 send_bit(1); // ID stuff send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID 6 send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID a send_bit(1); // ID 1 send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID 5 send_bit(1); // RTR send_bit(0); // r1 send_bit(0); // r0 send_bit(0); // DLC send_bit(1); // DLC send_bit(0); // DLC send_bit(1); // DLC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC 4 send_bit(1); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(1); // CRC d send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC 3 send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC 9 send_bit(1); // CRC DELIM send_bit(0); // ACK send_bit(1); // ACK DELIM send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // INTER send_bit(1); // INTER send_bit(1); // INTER end // repeat end join read_receive_buffer; release_rx_buffer_command; read_receive_buffer; release_rx_buffer_command; read_receive_buffer; // Read irq register #1 read_register(8'd3, tmp_data); // Read error code capture register read_register(8'd12, tmp_data); // Read error capture code register// read_register(8'd12, tmp_data);read_register(8'd14, tmp_data); // rx err cntread_register(8'd15, tmp_data); // tx err cnt #4000000; endendtask // manual_frame_exttask bus_off_test; // Testbench sends a frame begin write_register(8'd10, 8'he8); // Writing ID[10:3] = 0xe8 write_register(8'd11, 8'hb7); // Writing ID[2:0] = 0x5, rtr = 1, length = 7 write_register(8'd12, 8'h00); // data byte 1 write_register(8'd13, 8'h00); // data byte 2 write_register(8'd14, 8'h00); // data byte 3 write_register(8'd15, 8'h00); // data byte 4 write_register(8'd16, 8'h00); // data byte 5 write_register(8'd17, 8'h00); // data byte 6 write_register(8'd18, 8'h00); // data byte 7 write_register(8'd19, 8'h00); // data byte 8 fork begin tx_request_command; end begin #2000; repeat (16) begin send_bit(0); // SOF send_bit(1); // ID send_bit(1); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(1); // RTR send_bit(0); // IDE send_bit(0); // r0 send_bit(0); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC DELIM send_bit(1); // ACK ack error send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // INTER send_bit(1); // INTER send_bit(1); // INTER end // repeat // Node is error passive now. // Read irq register (error interrupt should be cleared now. read_register(8'd3, tmp_data);->igor; repeat (34) begin send_bit(0); // SOF send_bit(1); // ID send_bit(1); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(1); // RTR send_bit(0); // IDE send_bit(0); // r0 send_bit(0); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC DELIM send_bit(1); // ACK ack error send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(0); // ERROR send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // ERROR DELIM send_bit(1); // INTER send_bit(1); // INTER send_bit(1); // INTER send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND send_bit(1); // SUSPEND end // repeat->igor; // Node is bus-off now // Read irq register (error interrupt should be cleared now. read_register(8'd3, tmp_data); #100000; // Switch-off reset mode write_register(8'd0, {7'h0, ~(`CAN_MODE_RESET)}); repeat (64 * 11) begin send_bit(1); end // repeat // Read irq register (error interrupt should be cleared now. read_register(8'd3, tmp_data); repeat (64 * 11) begin send_bit(1); end // repeat // Read irq register (error interrupt should be cleared now. read_register(8'd3, tmp_data); end join fork begin tx_request_command; end begin #1100; send_bit(1); // To spend some time before transmitter is ready. repeat (1) begin send_bit(0); // SOF send_bit(1); // ID send_bit(1); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(0); // ID send_bit(0); // ID send_bit(1); // ID send_bit(0); // ID send_bit(1); // ID send_bit(1); // RTR send_bit(0); // IDE send_bit(0); // r0 send_bit(0); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // DLC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(0); // CRC send_bit(0); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC send_bit(1); // CRC DELIM send_bit(0); // ACK send_bit(1); // ACK DELIM send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // EOF send_bit(1); // INTER send_bit(1); // INTER send_bit(1); // INTER end // repeat end join read_receive_buffer; release_rx_buffer_command; read_receive_buffer; release_rx_buffer_command; read_receive_buffer; #4000000; receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc #1000000; endendtask // bus_off_testtask send_frame_basic; // CAN IP core sends frames begin write_register(8'd10, 8'hea); // Writing ID[10:3] = 0xea write_register(8'd11, 8'h28); // Writing ID[2:0] = 0x1, rtr = 0, length = 8 write_register(8'd12, 8'h56); // data byte 1 write_register(8'd13, 8'h78); // data byte 2 write_register(8'd14, 8'h9a); // data byte 3 write_register(8'd15, 8'hbc); // data byte 4 write_register(8'd16, 8'hde); // data byte 5 write_register(8'd17, 8'hf0); // data byte 6 write_register(8'd18, 8'h0f); // data byte 7 write_register(8'd19, 8'hed); // data byte 8 // Enable irqs (basic mode) write_register(8'd0, 8'h1e); fork begin #1100; $display("\n\nStart receiving data from CAN bus"); receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h1, 15'h30bb); // mode, rtr, id, length, crc receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h0, 15'h6cea); // mode, rtr, id, length, crc receive_frame(0, 0, {26'h00000e8, 3'h1}, 4'h2, 15'h2da1); // mode, rtr, id, length, crc receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h2, 15'h7b4a); // mode, rtr, id, length, crc receive_frame(0, 0, {26'h00000ee, 3'h1}, 4'h1, 15'h00c5); // mode, rtr, id, length, crc end begin tx_request_command; end begin wait (can_testbench.i_can_top.i_can_bsp.go_tx) // waiting for tx to start wait (~can_testbench.i_can_top.i_can_bsp.need_to_tx) // waiting for tx to finish tx_request_command; // start another tx end begin // Transmitting acknowledge (for first packet) wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point); #1 rx = 0; wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point); #1 rx = 1; // Transmitting acknowledge (for second packet) wait (can_testbench.i_can_top.i_can_bsp.tx_state & can_testbench.i_can_top.i_can_bsp.rx_ack & can_testbench.i_can_top.i_can_bsp.tx_point); #1 rx = 0; wait (can_testbench.i_can_top.i_can_bsp.rx_ack_lim & can_testbench.i_can_top.i_can_bsp.tx_point); #1 rx = 1; end⌨️ 快捷键说明
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