xljc.tan.rpt

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

; N/A   ; None         ; 3.080 ns   ; A    ; STATE.s6 ; CLK      ;
; N/A   ; None         ; 3.080 ns   ; A    ; STATE.s4 ; CLK      ;
; N/A   ; None         ; 3.078 ns   ; A    ; STATE.s3 ; CLK      ;
; N/A   ; None         ; 3.078 ns   ; A    ; STATE.s0 ; CLK      ;
; N/A   ; None         ; 3.071 ns   ; A    ; STATE.s2 ; CLK      ;
; N/A   ; None         ; 3.071 ns   ; A    ; STATE.s1 ; CLK      ;
+-------+--------------+------------+------+----------+----------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A   ; None         ; 6.022 ns   ; STATE.s8 ; OT ; CLK        ;
+-------+--------------+------------+----------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.832 ns ; A    ; STATE.s2 ; CLK      ;
; N/A           ; None        ; -2.832 ns ; A    ; STATE.s1 ; CLK      ;
; N/A           ; None        ; -2.839 ns ; A    ; STATE.s3 ; CLK      ;
; N/A           ; None        ; -2.839 ns ; A    ; STATE.s0 ; CLK      ;
; N/A           ; None        ; -2.841 ns ; A    ; STATE.s6 ; CLK      ;
; N/A           ; None        ; -2.841 ns ; A    ; STATE.s4 ; CLK      ;
; N/A           ; None        ; -2.842 ns ; A    ; STATE.s8 ; CLK      ;
; N/A           ; None        ; -2.842 ns ; A    ; STATE.s7 ; CLK      ;
; N/A           ; None        ; -2.849 ns ; A    ; STATE.s5 ; CLK      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 22 13:12:56 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off XLJC -c XLJC --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 500.0 MHz between source register "STATE.s8" and destination register "STATE.s1"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.642 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'
            Info: 2: + IC(0.259 ns) + CELL(0.228 ns) = 0.487 ns; Loc. = LCCOMB_X15_Y15_N0; Fanout = 1; COMB Node = 'STATE~100'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.642 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 1; REG Node = 'STATE.s1'
            Info: Total cell delay = 0.383 ns ( 59.66 % )
            Info: Total interconnect delay = 0.259 ns ( 40.34 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.461 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 1; REG Node = 'STATE.s1'
                Info: Total cell delay = 1.472 ns ( 59.81 % )
                Info: Total interconnect delay = 0.989 ns ( 40.19 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.461 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'
                Info: Total cell delay = 1.472 ns ( 59.81 % )
                Info: Total interconnect delay = 0.989 ns ( 40.19 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "STATE.s5" (data pin = "A", clock pin = "CLK") is 3.088 ns
    Info: + Longest pin to register delay is 5.459 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'A'
        Info: 2: + IC(4.140 ns) + CELL(0.357 ns) = 5.304 ns; Loc. = LCCOMB_X15_Y15_N26; Fanout = 1; COMB Node = 'STATE~96'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.459 ns; Loc. = LCFF_X15_Y15_N27; Fanout = 1; REG Node = 'STATE.s5'
        Info: Total cell delay = 1.319 ns ( 24.16 % )
        Info: Total interconnect delay = 4.140 ns ( 75.84 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N27; Fanout = 1; REG Node = 'STATE.s5'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
Info: tco from clock "CLK" to destination pin "OT" through register "STATE.s8" is 6.022 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.467 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'
        Info: 2: + IC(1.505 ns) + CELL(1.962 ns) = 3.467 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'OT'
        Info: Total cell delay = 1.962 ns ( 56.59 % )
        Info: Total interconnect delay = 1.505 ns ( 43.41 % )
Info: th for register "STATE.s2" (data pin = "A", clock pin = "CLK") is -2.832 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'STATE.s2'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.442 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'A'
        Info: 2: + IC(4.134 ns) + CELL(0.346 ns) = 5.287 ns; Loc. = LCCOMB_X15_Y15_N2; Fanout = 1; COMB Node = 'STATE~99'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.442 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'STATE.s2'
        Info: Total cell delay = 1.308 ns ( 24.04 % )
        Info: Total interconnect delay = 4.134 ns ( 75.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Oct 22 13:12:57 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01