xljc.tan.qmsg

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register STATE.s8 STATE.s1 500.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 500.0 MHz between source register \"STATE.s8\" and destination register \"STATE.s1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.642 ns + Longest register register " "Info: + Longest register to register delay is 0.642 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE.s8 1 REG LCFF_X15_Y15_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE.s8 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.228 ns) 0.487 ns STATE~100 2 COMB LCCOMB_X15_Y15_N0 1 " "Info: 2: + IC(0.259 ns) + CELL(0.228 ns) = 0.487 ns; Loc. = LCCOMB_X15_Y15_N0; Fanout = 1; COMB Node = 'STATE~100'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.487 ns" { STATE.s8 STATE~100 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.642 ns STATE.s1 3 REG LCFF_X15_Y15_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.642 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 1; REG Node = 'STATE.s1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { STATE~100 STATE.s1 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 59.66 % ) " "Info: Total cell delay = 0.383 ns ( 59.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.259 ns ( 40.34 % ) " "Info: Total interconnect delay = 0.259 ns ( 40.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.642 ns" { STATE.s8 STATE~100 STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "0.642 ns" { STATE.s8 {} STATE~100 {} STATE.s1 {} } { 0.000ns 0.259ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.461 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns STATE.s1 3 REG LCFF_X15_Y15_N1 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N1; Fanout = 1; REG Node = 'STATE.s1'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK~clkctrl STATE.s1 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s1 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.461 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns STATE.s8 3 REG LCFF_X15_Y15_N17 2 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s8 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s1 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s8 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.642 ns" { STATE.s8 STATE~100 STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "0.642 ns" { STATE.s8 {} STATE~100 {} STATE.s1 {} } { 0.000ns 0.259ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s1 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s8 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE.s1 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "" { STATE.s1 {} } {  } {  } "" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "STATE.s5 A CLK 3.088 ns register " "Info: tsu for register \"STATE.s5\" (data pin = \"A\", clock pin = \"CLK\") is 3.088 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.459 ns + Longest pin register " "Info: + Longest pin to register delay is 5.459 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns A 1 PIN PIN_H12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'A'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.140 ns) + CELL(0.357 ns) 5.304 ns STATE~96 2 COMB LCCOMB_X15_Y15_N26 1 " "Info: 2: + IC(4.140 ns) + CELL(0.357 ns) = 5.304 ns; Loc. = LCCOMB_X15_Y15_N26; Fanout = 1; COMB Node = 'STATE~96'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.497 ns" { A STATE~96 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.459 ns STATE.s5 3 REG LCFF_X15_Y15_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.459 ns; Loc. = LCFF_X15_Y15_N27; Fanout = 1; REG Node = 'STATE.s5'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { STATE~96 STATE.s5 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 24.16 % ) " "Info: Total cell delay = 1.319 ns ( 24.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.140 ns ( 75.84 % ) " "Info: Total interconnect delay = 4.140 ns ( 75.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.459 ns" { A STATE~96 STATE.s5 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.459 ns" { A {} A~combout {} STATE~96 {} STATE.s5 {} } { 0.000ns 0.000ns 4.140ns 0.000ns } { 0.000ns 0.807ns 0.357ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.461 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns STATE.s5 3 REG LCFF_X15_Y15_N27 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N27; Fanout = 1; REG Node = 'STATE.s5'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK~clkctrl STATE.s5 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s5 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s5 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.459 ns" { A STATE~96 STATE.s5 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.459 ns" { A {} A~combout {} STATE~96 {} STATE.s5 {} } { 0.000ns 0.000ns 4.140ns 0.000ns } { 0.000ns 0.807ns 0.357ns 0.155ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s5 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s5 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK OT STATE.s8 6.022 ns register " "Info: tco from clock \"CLK\" to destination pin \"OT\" through register \"STATE.s8\" is 6.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.461 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns STATE.s8 3 REG LCFF_X15_Y15_N17 2 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s8 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.467 ns + Longest register pin " "Info: + Longest register to pin delay is 3.467 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns STATE.s8 1 REG LCFF_X15_Y15_N17 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N17; Fanout = 2; REG Node = 'STATE.s8'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATE.s8 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.505 ns) + CELL(1.962 ns) 3.467 ns OT 2 PIN PIN_Y13 0 " "Info: 2: + IC(1.505 ns) + CELL(1.962 ns) = 3.467 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'OT'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.467 ns" { STATE.s8 OT } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.962 ns ( 56.59 % ) " "Info: Total cell delay = 1.962 ns ( 56.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns ( 43.41 % ) " "Info: Total interconnect delay = 1.505 ns ( 43.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.467 ns" { STATE.s8 OT } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "3.467 ns" { STATE.s8 {} OT {} } { 0.000ns 1.505ns } { 0.000ns 1.962ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s8 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s8 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.467 ns" { STATE.s8 OT } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "3.467 ns" { STATE.s8 {} OT {} } { 0.000ns 1.505ns } { 0.000ns 1.962ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "STATE.s2 A CLK -2.832 ns register " "Info: th for register \"STATE.s2\" (data pin = \"A\", clock pin = \"CLK\") is -2.832 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.461 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns CLK 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'CLK'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns CLK~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns STATE.s2 3 REG LCFF_X15_Y15_N3 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'STATE.s2'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s2 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.442 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns A 1 PIN PIN_H12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'A'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { A } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.134 ns) + CELL(0.346 ns) 5.287 ns STATE~99 2 COMB LCCOMB_X15_Y15_N2 1 " "Info: 2: + IC(4.134 ns) + CELL(0.346 ns) = 5.287 ns; Loc. = LCCOMB_X15_Y15_N2; Fanout = 1; COMB Node = 'STATE~99'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.480 ns" { A STATE~99 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.442 ns STATE.s2 3 REG LCFF_X15_Y15_N3 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.442 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'STATE.s2'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { STATE~99 STATE.s2 } "NODE_NAME" } } { "XLJC.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/XLJC/XLJC.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.308 ns ( 24.04 % ) " "Info: Total cell delay = 1.308 ns ( 24.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.134 ns ( 75.96 % ) " "Info: Total interconnect delay = 4.134 ns ( 75.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.442 ns" { A STATE~99 STATE.s2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.442 ns" { A {} A~combout {} STATE~99 {} STATE.s2 {} } { 0.000ns 0.000ns 4.134ns 0.000ns } { 0.000ns 0.807ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { CLK CLK~clkctrl STATE.s2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { CLK {} CLK~combout {} CLK~clkctrl {} STATE.s2 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.442 ns" { A STATE~99 STATE.s2 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.442 ns" { A {} A~combout {} STATE~99 {} STATE.s2 {} } { 0.000ns 0.000ns 4.134ns 0.000ns } { 0.000ns 0.807ns 0.346ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}