vhdl2.eda.rpt

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

EDA Netlist Writer report for vhdl2
Wed Oct 22 13:06:19 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------+
; EDA Netlist Writer Summary                                                       ;
+---------------------------+------------------------------------------------------+
; EDA Netlist Writer Status ; No Output Files Generated - Wed Oct 22 13:06:19 2008 ;
; Revision Name             ; vhdl2                                                ;
; Top-level Entity Name     ; vhdl2                                                ;
; Family                    ; Stratix II                                           ;
+---------------------------+------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 22 13:06:19 2008
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off vhdl2 -c vhdl2
Warning: Can't generate output files. Specify command-line options to generate output files, or update EDA tool settings using GUI or Tcl script.
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 112 megabytes
    Info: Processing ended: Wed Oct 22 13:06:20 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01