vhdl2.tan.qmsg

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register reg\[2\] reg\[3\] 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"reg\[2\]\" and destination register \"reg\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.567 ns + Longest register register " "Info: + Longest register to register delay is 0.567 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg\[2\] 1 REG LCFF_X15_Y15_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N29; Fanout = 1; REG Node = 'reg\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg[2] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.053 ns) 0.412 ns reg~110 2 COMB LCCOMB_X15_Y15_N30 1 " "Info: 2: + IC(0.359 ns) + CELL(0.053 ns) = 0.412 ns; Loc. = LCCOMB_X15_Y15_N30; Fanout = 1; COMB Node = 'reg~110'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.412 ns" { reg[2] reg~110 } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.567 ns reg\[3\] 3 REG LCFF_X15_Y15_N31 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.567 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 1; REG Node = 'reg\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { reg~110 reg[3] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.208 ns ( 36.68 % ) " "Info: Total cell delay = 0.208 ns ( 36.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.359 ns ( 63.32 % ) " "Info: Total interconnect delay = 0.359 ns ( 63.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { reg[2] reg~110 reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "0.567 ns" { reg[2] {} reg~110 {} reg[3] {} } { 0.000ns 0.359ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.461 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns reg\[3\] 3 REG LCFF_X15_Y15_N31 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 1; REG Node = 'reg\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { clk~clkctrl reg[3] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[3] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.461 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns reg\[2\] 3 REG LCFF_X15_Y15_N29 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N29; Fanout = 1; REG Node = 'reg\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { clk~clkctrl reg[2] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[2] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[3] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[2] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { reg[2] reg~110 reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "0.567 ns" { reg[2] {} reg~110 {} reg[3] {} } { 0.000ns 0.359ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[3] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[2] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "" { reg[3] {} } {  } {  } "" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "reg\[6\] clr clk 3.091 ns register " "Info: tsu for register \"reg\[6\]\" (data pin = \"clr\", clock pin = \"clk\") is 3.091 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.462 ns + Longest pin register " "Info: + Longest pin to register delay is 5.462 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns clr 1 PIN PIN_H12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'clr'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.143 ns) + CELL(0.357 ns) 5.307 ns reg~107 2 COMB LCCOMB_X15_Y15_N20 1 " "Info: 2: + IC(4.143 ns) + CELL(0.357 ns) = 5.307 ns; Loc. = LCCOMB_X15_Y15_N20; Fanout = 1; COMB Node = 'reg~107'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { clr reg~107 } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.462 ns reg\[6\] 3 REG LCFF_X15_Y15_N21 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.462 ns; Loc. = LCFF_X15_Y15_N21; Fanout = 1; REG Node = 'reg\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { reg~107 reg[6] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 24.15 % ) " "Info: Total cell delay = 1.319 ns ( 24.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.143 ns ( 75.85 % ) " "Info: Total interconnect delay = 4.143 ns ( 75.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.462 ns" { clr reg~107 reg[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.462 ns" { clr {} clr~combout {} reg~107 {} reg[6] {} } { 0.000ns 0.000ns 4.143ns 0.000ns } { 0.000ns 0.807ns 0.357ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.461 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns reg\[6\] 3 REG LCFF_X15_Y15_N21 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N21; Fanout = 1; REG Node = 'reg\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { clk~clkctrl reg[6] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.462 ns" { clr reg~107 reg[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.462 ns" { clr {} clr~combout {} reg~107 {} reg[6] {} } { 0.000ns 0.000ns 4.143ns 0.000ns } { 0.000ns 0.807ns 0.357ns 0.155ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[6] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout dout~reg0 5.980 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\" through register \"dout~reg0\" is 5.980 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.461 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns dout~reg0 3 REG LCFF_X15_Y15_N19 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { clk~clkctrl dout~reg0 } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl dout~reg0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} dout~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.425 ns + Longest register pin " "Info: + Longest register to pin delay is 3.425 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout~reg0 1 REG LCFF_X15_Y15_N19 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout~reg0 } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.463 ns) + CELL(1.962 ns) 3.425 ns dout 2 PIN PIN_Y13 0 " "Info: 2: + IC(1.463 ns) + CELL(1.962 ns) = 3.425 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'dout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { dout~reg0 dout } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.962 ns ( 57.28 % ) " "Info: Total cell delay = 1.962 ns ( 57.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.463 ns ( 42.72 % ) " "Info: Total interconnect delay = 1.463 ns ( 42.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { dout~reg0 dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "3.425 ns" { dout~reg0 {} dout {} } { 0.000ns 1.463ns } { 0.000ns 1.962ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl dout~reg0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} dout~reg0 {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.425 ns" { dout~reg0 dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "3.425 ns" { dout~reg0 {} dout {} } { 0.000ns 1.463ns } { 0.000ns 1.962ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "reg\[1\] clr clk -2.832 ns register " "Info: th for register \"reg\[1\]\" (data pin = \"clr\", clock pin = \"clk\") is -2.832 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.461 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.646 ns) + CELL(0.618 ns) 2.461 ns reg\[1\] 3 REG LCFF_X15_Y15_N3 1 " "Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'reg\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.264 ns" { clk~clkctrl reg[1] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.81 % ) " "Info: Total cell delay = 1.472 ns ( 59.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 40.19 % ) " "Info: Total interconnect delay = 0.989 ns ( 40.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[1] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.442 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.442 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.807 ns) 0.807 ns clr 1 PIN PIN_H12 9 " "Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'clr'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.134 ns) + CELL(0.346 ns) 5.287 ns reg~112 2 COMB LCCOMB_X15_Y15_N2 1 " "Info: 2: + IC(4.134 ns) + CELL(0.346 ns) = 5.287 ns; Loc. = LCCOMB_X15_Y15_N2; Fanout = 1; COMB Node = 'reg~112'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.480 ns" { clr reg~112 } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.442 ns reg\[1\] 3 REG LCFF_X15_Y15_N3 1 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.442 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'reg\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { reg~112 reg[1] } "NODE_NAME" } } { "vhdl2.vhd" "" { Text "C:/Documents and Settings/dell/My Documents/vhdl2/vhdl2.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.308 ns ( 24.04 % ) " "Info: Total cell delay = 1.308 ns ( 24.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.134 ns ( 75.96 % ) " "Info: Total interconnect delay = 4.134 ns ( 75.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.442 ns" { clr reg~112 reg[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.442 ns" { clr {} clr~combout {} reg~112 {} reg[1] {} } { 0.000ns 0.000ns 4.134ns 0.000ns } { 0.000ns 0.807ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.461 ns" { clk clk~clkctrl reg[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.461 ns" { clk {} clk~combout {} clk~clkctrl {} reg[1] {} } { 0.000ns 0.000ns 0.343ns 0.646ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.442 ns" { clr reg~112 reg[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.442 ns" { clr {} clr~combout {} reg~112 {} reg[1] {} } { 0.000ns 0.000ns 4.134ns 0.000ns } { 0.000ns 0.807ns 0.346ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}