vhdl2.hier_info

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

|vhdl2
clk => dout~reg0.CLK
clk => reg[7].CLK
clk => reg[6].CLK
clk => reg[5].CLK
clk => reg[4].CLK
clk => reg[3].CLK
clk => reg[2].CLK
clk => reg[1].CLK
clk => reg[0].CLK
clr => reg~7.OUTPUTSELECT
clr => reg~6.OUTPUTSELECT
clr => reg~5.OUTPUTSELECT
clr => reg~4.OUTPUTSELECT
clr => reg~3.OUTPUTSELECT
clr => reg~2.OUTPUTSELECT
clr => reg~1.OUTPUTSELECT
clr => reg~0.OUTPUTSELECT
clr => dout~0.OUTPUTSELECT
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE