vhdl2.tan.rpt

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

; N/A   ; None         ; 3.078 ns   ; clr  ; reg[2]    ; clk      ;
; N/A   ; None         ; 3.077 ns   ; clr  ; reg[5]    ; clk      ;
; N/A   ; None         ; 3.077 ns   ; clr  ; reg[4]    ; clk      ;
; N/A   ; None         ; 3.071 ns   ; clr  ; reg[1]    ; clk      ;
; N/A   ; None         ; 3.071 ns   ; clr  ; reg[0]    ; clk      ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 5.980 ns   ; dout~reg0 ; dout ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -2.832 ns ; clr  ; reg[1]    ; clk      ;
; N/A           ; None        ; -2.832 ns ; clr  ; reg[0]    ; clk      ;
; N/A           ; None        ; -2.838 ns ; clr  ; reg[5]    ; clk      ;
; N/A           ; None        ; -2.838 ns ; clr  ; reg[4]    ; clk      ;
; N/A           ; None        ; -2.839 ns ; clr  ; reg[3]    ; clk      ;
; N/A           ; None        ; -2.839 ns ; clr  ; reg[2]    ; clk      ;
; N/A           ; None        ; -2.842 ns ; clr  ; dout~reg0 ; clk      ;
; N/A           ; None        ; -2.842 ns ; clr  ; reg[7]    ; clk      ;
; N/A           ; None        ; -2.852 ns ; clr  ; reg[6]    ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 22 13:06:09 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vhdl2 -c vhdl2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "reg[2]" and destination register "reg[3]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.567 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N29; Fanout = 1; REG Node = 'reg[2]'
            Info: 2: + IC(0.359 ns) + CELL(0.053 ns) = 0.412 ns; Loc. = LCCOMB_X15_Y15_N30; Fanout = 1; COMB Node = 'reg~110'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.567 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 1; REG Node = 'reg[3]'
            Info: Total cell delay = 0.208 ns ( 36.68 % )
            Info: Total interconnect delay = 0.359 ns ( 63.32 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.461 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N31; Fanout = 1; REG Node = 'reg[3]'
                Info: Total cell delay = 1.472 ns ( 59.81 % )
                Info: Total interconnect delay = 0.989 ns ( 40.19 % )
            Info: - Longest clock path from clock "clk" to source register is 2.461 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N29; Fanout = 1; REG Node = 'reg[2]'
                Info: Total cell delay = 1.472 ns ( 59.81 % )
                Info: Total interconnect delay = 0.989 ns ( 40.19 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "reg[6]" (data pin = "clr", clock pin = "clk") is 3.091 ns
    Info: + Longest pin to register delay is 5.462 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'clr'
        Info: 2: + IC(4.143 ns) + CELL(0.357 ns) = 5.307 ns; Loc. = LCCOMB_X15_Y15_N20; Fanout = 1; COMB Node = 'reg~107'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.462 ns; Loc. = LCFF_X15_Y15_N21; Fanout = 1; REG Node = 'reg[6]'
        Info: Total cell delay = 1.319 ns ( 24.15 % )
        Info: Total interconnect delay = 4.143 ns ( 75.85 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N21; Fanout = 1; REG Node = 'reg[6]'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
Info: tco from clock "clk" to destination pin "dout" through register "dout~reg0" is 5.980 ns
    Info: + Longest clock path from clock "clk" to source register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 1; REG Node = 'dout~reg0'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.425 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y15_N19; Fanout = 1; REG Node = 'dout~reg0'
        Info: 2: + IC(1.463 ns) + CELL(1.962 ns) = 3.425 ns; Loc. = PIN_Y13; Fanout = 0; PIN Node = 'dout'
        Info: Total cell delay = 1.962 ns ( 57.28 % )
        Info: Total interconnect delay = 1.463 ns ( 42.72 % )
Info: th for register "reg[1]" (data pin = "clr", clock pin = "clk") is -2.832 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.461 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.646 ns) + CELL(0.618 ns) = 2.461 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'reg[1]'
        Info: Total cell delay = 1.472 ns ( 59.81 % )
        Info: Total interconnect delay = 0.989 ns ( 40.19 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.442 ns
        Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_H12; Fanout = 9; PIN Node = 'clr'
        Info: 2: + IC(4.134 ns) + CELL(0.346 ns) = 5.287 ns; Loc. = LCCOMB_X15_Y15_N2; Fanout = 1; COMB Node = 'reg~112'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.442 ns; Loc. = LCFF_X15_Y15_N3; Fanout = 1; REG Node = 'reg[1]'
        Info: Total cell delay = 1.308 ns ( 24.04 % )
        Info: Total interconnect delay = 4.134 ns ( 75.96 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Oct 22 13:06:11 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01