vhdl2.vhd

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vhdl2 is
port(clk:in std_logic;
clr:in std_logic;
dout:out std_logic);
end;
architecture one of vhdl2 is
signal reg:std_logic_vector(7 downto 0);
begin
process(clk,clr)
begin
if clk'event and clk='1'then
if clr='1'then
dout<='0';
reg<="01001111";
else
dout<=reg(7);
reg<=reg(6 downto 0)&reg(7);
end if;
end if;
end process;
end;