seg7dec.map.summary

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

Analysis & Synthesis Status : Successful - Wed Oct 22 12:49:21 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : seg7dec
Top-level Entity Name : seg7dec
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 6
    Dedicated logic registers : 0
Total registers : 0
Total pins : 11
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0