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📄 seg7dec.tan.rpt

📁 EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.
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Classic Timing Analyzer report for seg7dec
Wed Oct 22 12:49:35 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                          ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From     ; To        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 9.390 ns    ; bcdin[2] ; segout[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;          ;           ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+----------+-----------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------+
; tpd                                                                ;
+-------+-------------------+-----------------+----------+-----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From     ; To        ;
+-------+-------------------+-----------------+----------+-----------+
; N/A   ; None              ; 9.390 ns        ; bcdin[2] ; segout[0] ;
; N/A   ; None              ; 9.240 ns        ; bcdin[2] ; segout[1] ;
; N/A   ; None              ; 8.958 ns        ; bcdin[2] ; segout[2] ;
; N/A   ; None              ; 8.889 ns        ; bcdin[2] ; segout[6] ;
; N/A   ; None              ; 8.881 ns        ; bcdin[2] ; segout[5] ;
; N/A   ; None              ; 8.876 ns        ; bcdin[2] ; segout[3] ;
; N/A   ; None              ; 8.700 ns        ; bcdin[0] ; segout[0] ;
; N/A   ; None              ; 8.551 ns        ; bcdin[0] ; segout[1] ;
; N/A   ; None              ; 8.268 ns        ; bcdin[0] ; segout[2] ;
; N/A   ; None              ; 8.206 ns        ; bcdin[0] ; segout[6] ;
; N/A   ; None              ; 8.192 ns        ; bcdin[0] ; segout[3] ;
; N/A   ; None              ; 8.190 ns        ; bcdin[0] ; segout[5] ;
; N/A   ; None              ; 7.977 ns        ; bcdin[1] ; segout[0] ;
; N/A   ; None              ; 7.828 ns        ; bcdin[1] ; segout[1] ;
; N/A   ; None              ; 7.709 ns        ; bcdin[3] ; segout[1] ;
; N/A   ; None              ; 7.492 ns        ; bcdin[1] ; segout[6] ;
; N/A   ; None              ; 7.478 ns        ; bcdin[1] ; segout[3] ;
; N/A   ; None              ; 7.468 ns        ; bcdin[1] ; segout[5] ;
; N/A   ; None              ; 7.415 ns        ; bcdin[1] ; segout[2] ;
; N/A   ; None              ; 7.397 ns        ; bcdin[3] ; segout[2] ;
; N/A   ; None              ; 7.375 ns        ; bcdin[3] ; segout[6] ;
; N/A   ; None              ; 7.318 ns        ; bcdin[3] ; segout[5] ;
+-------+-------------------+-----------------+----------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Wed Oct 22 12:49:35 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg7dec -c seg7dec --timing_analysis_only
Info: Longest tpd from source pin "bcdin[2]" to destination pin "segout[0]" is 9.390 ns
    Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_D3; Fanout = 6; PIN Node = 'bcdin[2]'
    Info: 2: + IC(5.530 ns) + CELL(0.053 ns) = 6.440 ns; Loc. = LCCOMB_X6_Y2_N16; Fanout = 1; COMB Node = 'Mux5~18'
    Info: 3: + IC(0.988 ns) + CELL(1.962 ns) = 9.390 ns; Loc. = PIN_W13; Fanout = 0; PIN Node = 'segout[0]'
    Info: Total cell delay = 2.872 ns ( 30.59 % )
    Info: Total interconnect delay = 6.518 ns ( 69.41 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Wed Oct 22 12:49:36 2008
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


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