xljc.vhd

EDA实验3个经典程序及图形仿真文件和实验报告,对实验参考绝对有益处.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XLJC IS
   PORT (A,CLK,CLR : IN STD_LOGIC;
          OT : OUT STD_LOGIC);
END;
ARCHITECTURE VHDL OF XLJC IS 
   TYPE STATE_TYPE IS (s0, s1, s2, S3, S4, S5, S6, S7, S8);
   SIGNAL STATE : STATE_TYPE;
BEGIN 
   PROCESS (STATE)
    BEGIN
      CASE state IS
      WHEN S8 => OT <= '1';
      WHEN OTHERS => OT<='0';
      END CASE;
   END PROCESS;
   PROCESS (CLK, CLR)
    BEGIN
     IF CLR = '1' THEN
        state <= s0;
     ELSIF (clk'EVENT AND clk = '1') THEN
      CASE state IS 
       WHEN S0 => IF A='1' THEN STATE<=S1;ELSE state <= s0; END IF;
       WHEN S1 => IF A='1' THEN STATE<=S2;ELSE state <= s0; END IF;
       WHEN S2 => IF A='1' THEN STATE<=S3;ELSE state <= s0; END IF;
       WHEN S3 => IF A='0' THEN STATE<=S4;ELSE state <= s0; END IF;
       WHEN S4 => IF A='0' THEN STATE<=S5;ELSE state <= s0; END IF;
       WHEN S5 => IF A='1' THEN STATE<=S6;ELSE state <= s0; END IF;
       WHEN S6 => IF A='0' THEN STATE<=S7;ELSE state <= s0; END IF;
       WHEN S7 => IF A='1' THEN STATE<=S8;ELSE state <= s0; END IF;
       WHEN S8 => IF A='1' THEN STATE<=S1;ELSE state <= s0; END IF;
      END CASE;
     END IF;
    END PROCESS; 
END VHDL;