hdefs.c

unix下调试内存泄露的工具源代码

      ppHRegPPC32(i->Pin.FpF64toF32.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.FpF64toF32.src);
      return;
   case Pin_FpF64toI32:
      vex_printf("fctiw %%fr7,");
      ppHRegPPC32(i->Pin.FpF64toI32.src);
      vex_printf("; stfiwx %%fr7,%%r0,%%r1");
      vex_printf("; lwzx ");
      ppHRegPPC32(i->Pin.FpF64toI32.dst);
      vex_printf(",%%r0,%%r1");
      return;
   case Pin_FpCMov:
      vex_printf("fpcmov (%s) ", showPPC32CondCode(i->Pin.FpCMov.cond));
      ppHRegPPC32(i->Pin.FpCMov.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.FpCMov.src);
      vex_printf(": ");
      vex_printf("if (fr_dst != fr_src) { ");
      if (i->Pin.FpCMov.cond.test != Pct_ALWAYS) {
         vex_printf("if (%s) { ", showPPC32CondCode(i->Pin.FpCMov.cond));
      }
      vex_printf("fmr ");
      ppHRegPPC32(i->Pin.FpCMov.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.FpCMov.src);
      if (i->Pin.FpCMov.cond.test != Pct_ALWAYS)
         vex_printf(" }");
      vex_printf(" }");
      return;
   case Pin_FpLdFPSCR:
      vex_printf("mtfsf 0xFF,");
      ppHRegPPC32(i->Pin.FpLdFPSCR.src);
      return;
   case Pin_FpCmp:
      vex_printf("fcmpo %%cr1,");
      ppHRegPPC32(i->Pin.FpCmp.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.FpCmp.srcR);
      vex_printf("; mfcr ");
      ppHRegPPC32(i->Pin.FpCmp.dst);
      vex_printf("; rlwinm ");
      ppHRegPPC32(i->Pin.FpCmp.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.FpCmp.dst);
      vex_printf(",8,28,31");
      return;

   case Pin_RdWrLR:
      vex_printf("%s ", i->Pin.RdWrLR.wrLR ? "mtlr" : "mflr");
      ppHRegPPC32(i->Pin.RdWrLR.gpr);
      return;

   case Pin_AvLdSt: {
      UChar sz = i->Pin.AvLdSt.sz;
      if (i->Pin.AvLdSt.addr->tag == Pam_IR) {
         ppLoadImm(hregPPC32_GPR30(), i->Pin.AvLdSt.addr->Pam.RR.index);
         vex_printf(" ; ");
      }
      if (i->Pin.AvLdSt.isLoad)
         vex_printf("lv%sx ", sz==8 ? "eb" : sz==16 ? "eh" : sz==32 ? "ew" : "");
      else
         vex_printf("stv%sx ", sz==8 ? "eb" : sz==16 ? "eh" : sz==32 ? "ew" : "");
      ppHRegPPC32(i->Pin.AvLdSt.reg);
      vex_printf(",");
      if (i->Pin.AvLdSt.addr->tag == Pam_IR)
         vex_printf("%%r30");
      else 
         ppHRegPPC32(i->Pin.AvLdSt.addr->Pam.RR.index);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvLdSt.addr->Pam.RR.base);
      return;
   }
   case Pin_AvUnary:
      vex_printf("%s ", showPPC32AvOp(i->Pin.AvUnary.op));
      ppHRegPPC32(i->Pin.AvUnary.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvUnary.src);
      return;
   case Pin_AvBinary:
      vex_printf("%s ", showPPC32AvOp(i->Pin.AvBinary.op));
      ppHRegPPC32(i->Pin.AvBinary.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBinary.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBinary.srcR);
      return;
   case Pin_AvBin8x16:
      vex_printf("%s(b) ", showPPC32AvOp(i->Pin.AvBin8x16.op));
      ppHRegPPC32(i->Pin.AvBin8x16.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin8x16.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin8x16.srcR);
      return;
   case Pin_AvBin16x8:
      vex_printf("%s(h) ", showPPC32AvOp(i->Pin.AvBin16x8.op));
      ppHRegPPC32(i->Pin.AvBin16x8.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin16x8.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin16x8.srcR);
      return;
   case Pin_AvBin32x4:
      vex_printf("%s(w) ", showPPC32AvOp(i->Pin.AvBin32x4.op));
      ppHRegPPC32(i->Pin.AvBin32x4.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin32x4.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin32x4.srcR);
      return;
   case Pin_AvBin32Fx4:
      vex_printf("%s ", showPPC32AvOp(i->Pin.AvBin32Fx4.op));
      ppHRegPPC32(i->Pin.AvBin32Fx4.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin32Fx4.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvBin32Fx4.srcR);
      return;
   case Pin_AvPerm:
      vex_printf("vperm ");
      ppHRegPPC32(i->Pin.AvPerm.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvPerm.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvPerm.srcR);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvPerm.ctl);
      return;

   case Pin_AvSel:
      vex_printf("vsel ");
      ppHRegPPC32(i->Pin.AvSel.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvSel.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvSel.srcR);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvSel.ctl);
      return;

   case Pin_AvShlDbl:
      vex_printf("vsldoi ");
      ppHRegPPC32(i->Pin.AvShlDbl.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvShlDbl.srcL);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvShlDbl.srcR);
      vex_printf(",%d", i->Pin.AvShlDbl.shift);
      return;

   case Pin_AvSplat: {
      UChar ch_sz = toUChar(
                       (i->Pin.AvSplat.sz == 8) ? 'b' :
                       (i->Pin.AvSplat.sz == 16) ? 'h' : 'w'
                    );
      vex_printf("vsplt%s%c ",
                 i->Pin.AvSplat.src->tag == Pri_Imm ? "is" : "", ch_sz);
      ppHRegPPC32(i->Pin.AvSplat.dst);
      vex_printf(",");
      if (i->Pin.AvSplat.src->tag == Pri_Imm) {
         vex_printf("%d", (Char)(i->Pin.AvSplat.src->Pri.Imm));
      } else {
         ppHRegPPC32(i->Pin.AvSplat.src->Pri.Reg);
         vex_printf(", 0");
      }
      return;
   }

   case Pin_AvCMov:
      vex_printf("avcmov (%s) ", showPPC32CondCode(i->Pin.AvCMov.cond));
      ppHRegPPC32(i->Pin.AvCMov.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvCMov.src);
      vex_printf(": ");
      vex_printf("if (v_dst != v_src) { ");
      if (i->Pin.AvCMov.cond.test != Pct_ALWAYS) {
         vex_printf("if (%s) { ", showPPC32CondCode(i->Pin.AvCMov.cond));
      }
      vex_printf("vmr ");
      ppHRegPPC32(i->Pin.AvCMov.dst);
      vex_printf(",");
      ppHRegPPC32(i->Pin.AvCMov.src);
      if (i->Pin.FpCMov.cond.test != Pct_ALWAYS)
         vex_printf(" }");
      vex_printf(" }");
      return;

   case Pin_AvLdVSCR:
      vex_printf("mtvscr ");
      ppHRegPPC32(i->Pin.AvLdVSCR.src);
      return;

   default:
      vex_printf("\nppPPC32Instr(ppc32): No such tag(%d)\n", (Int)i->tag);
      vpanic("ppPPC32Instr(ppc32)");
   }
}

/* --------- Helpers for register allocation. --------- */

void getRegUsage_PPC32Instr ( HRegUsage* u, PPC32Instr* i )
{
   initHRegUsage(u);
   switch (i->tag) {
   case Pin_LI32:
      addHRegUse(u, HRmWrite, i->Pin.LI32.dst);
      break;
   case Pin_Alu32:
      addHRegUse(u, HRmRead, i->Pin.Alu32.srcL);
      addRegUsage_PPC32RH(u, i->Pin.Alu32.srcR);
      addHRegUse(u, HRmWrite, i->Pin.Alu32.dst);
      return;
   case Pin_Cmp32:
      addHRegUse(u, HRmRead, i->Pin.Cmp32.srcL);
      addRegUsage_PPC32RH(u, i->Pin.Cmp32.srcR);
      return;
   case Pin_Unary32:
      addHRegUse(u, HRmWrite, i->Pin.Unary32.dst);
      addHRegUse(u, HRmRead, i->Pin.Unary32.src);
      return;
   case Pin_MulL:
      addHRegUse(u, HRmWrite, i->Pin.MulL.dst);
      addHRegUse(u, HRmRead, i->Pin.MulL.srcL);
      addHRegUse(u, HRmRead, i->Pin.MulL.srcR);
      return;
   case Pin_Div:
      addHRegUse(u, HRmWrite, i->Pin.Div.dst);
      addHRegUse(u, HRmRead, i->Pin.Div.srcL);
      addHRegUse(u, HRmRead, i->Pin.Div.srcR);
      return;
   case Pin_Call:
      /* This is a bit subtle. */
      /* First off, claim it trashes all the caller-saved regs
         which fall within the register allocator's jurisdiction.
         These I believe to be: r3 to r12.
      */
      addHRegUse(u, HRmWrite, hregPPC32_GPR3());
      addHRegUse(u, HRmWrite, hregPPC32_GPR4());
      addHRegUse(u, HRmWrite, hregPPC32_GPR5());
      addHRegUse(u, HRmWrite, hregPPC32_GPR6());
      addHRegUse(u, HRmWrite, hregPPC32_GPR7());
      addHRegUse(u, HRmWrite, hregPPC32_GPR8());
      addHRegUse(u, HRmWrite, hregPPC32_GPR9());
      addHRegUse(u, HRmWrite, hregPPC32_GPR10());
      addHRegUse(u, HRmWrite, hregPPC32_GPR11());
      addHRegUse(u, HRmWrite, hregPPC32_GPR12());
      
      /* Now we have to state any parameter-carrying registers
         which might be read.  This depends on the regparmness. */
      switch (i->Pin.Call.regparms) {
      case  8: addHRegUse(u, HRmRead, hregPPC32_GPR10()); /*fallthru*/
      case  7: addHRegUse(u, HRmRead, hregPPC32_GPR9() ); /*fallthru*/
      case  6: addHRegUse(u, HRmRead, hregPPC32_GPR8() ); /*fallthru*/
      case  5: addHRegUse(u, HRmRead, hregPPC32_GPR7() ); /*fallthru*/
      case  4: addHRegUse(u, HRmRead, hregPPC32_GPR6() ); /*fallthru*/
      case  3: addHRegUse(u, HRmRead, hregPPC32_GPR5() ); /*fallthru*/
      case  2: addHRegUse(u, HRmRead, hregPPC32_GPR4() ); /*fallthru*/
      case  1: addHRegUse(u, HRmRead, hregPPC32_GPR3() ); /*fallthru*/
      case  0: break;
      default: vpanic("getRegUsage_PPC32Instr:Call:regparms");
      }
      /* Finally, there is the issue that the insn trashes a
         register because the literal target address has to be
         loaded into a register.  %r12 seems a suitable victim.
         (Can't use %r0, as use ops that interpret it as value zero).  */
      addHRegUse(u, HRmWrite, hregPPC32_GPR12());
      /* Upshot of this is that the assembler really must use %r12,
         and no other, as a destination temporary. */
      return;
   case Pin_Goto:
      addRegUsage_PPC32RI(u, i->Pin.Goto.dst);
      /* GPR3 holds destination address from Pin_Goto */
      addHRegUse(u, HRmWrite, hregPPC32_GPR3());
      if (i->Pin.Goto.jk != Ijk_Boring)
         addHRegUse(u, HRmWrite, GuestStatePtr);
      return;
   case Pin_CMov32:
      addRegUsage_PPC32RI(u, i->Pin.CMov32.src);
      addHRegUse(u, HRmWrite, i->Pin.CMov32.dst);
      return;
   case Pin_Load:
      addRegUsage_PPC32AMode(u, i->Pin.Load.src);
      addHRegUse(u, HRmWrite, i->Pin.Load.dst);
      return;
   case Pin_Store:
      addHRegUse(u, HRmRead, i->Pin.Store.src);
      addRegUsage_PPC32AMode(u, i->Pin.Store.dst);
      return;
   case Pin_Set32:
      addHRegUse(u, HRmWrite, i->Pin.Set32.dst);
      return;
   case Pin_MfCR:
      addHRegUse(u, HRmWrite, i->Pin.MfCR.dst);
      return;
   case Pin_MFence:
      return;

   case Pin_FpUnary:
      addHRegUse(u, HRmWrite, i->Pin.FpUnary.dst);
      addHRegUse(u, HRmRead,  i->Pin.FpUnary.src);
      return;
   case Pin_FpBinary:
      addHRegUse(u, HRmWrite, i->Pin.FpBinary.dst);
      addHRegUse(u, HRmRead,  i->Pin.FpBinary.srcL);
      addHRegUse(u, HRmRead,  i->Pin.FpBinary.srcR);
      return;
   case Pin_FpLdSt:
      addHRegUse(u, (i->Pin.FpLdSt.isLoad ? HRmWrite : HRmRead),
                 i->Pin.FpLdSt.reg);
      addRegUsage_PPC32AMode(u, i->Pin.FpLdSt.addr);
      return;
   case Pin_FpF64toF32:
      addHRegUse(u, HRmWrite, i->Pin.FpF64toF32.dst);
      addHRegUse(u, HRmRead,  i->Pin.FpF64toF32.src);
      return;
   case Pin_FpF64toI32:
      addHRegUse(u, HRmWrite,  i->Pin.FpF64toI32.dst);
      addHRegUse(u, HRmWrite, hregPPC32_FPR7());
      addHRegUse(u, HRmRead,   i->Pin.FpF64toI32.src);
      return;
   case Pin_FpCMov:
      addHRegUse(u, HRmModify, i->Pin.FpCMov.dst);
      addHRegUse(u, HRmRead, i->Pin.FpCMov.src);
      return;
   case Pin_FpLdFPSCR:
      addHRegUse(u, HRmRead, i->Pin.FpLdFPSCR.src);
      return;
   case Pin_FpCmp:
      addHRegUse(u, HRmWrite, i->Pin.FpCmp.dst);
      addHRegUse(u, HRmRead,   i->Pin.FpCmp.srcL);
      addHRegUse(u, HRmRead,   i->Pin.FpCmp.srcR);
      return;

   case Pin_RdWrLR:
      addHRegUse(u, (i->Pin.RdWrLR.wrLR ? HRmRead : HRmWrite),
                 i->Pin.RdWrLR.gpr);
      return;

   case Pin_AvLdSt:
      addHRegUse(u, (i->Pin.AvLdSt.isLoad ? HRmWrite : HRmRead),
                 i->Pin.AvLdSt.reg);
      if (i->Pin.AvLdSt.addr->tag == Pam_IR)
         addHRegUse(u, HRmWrite, hregPPC32_GPR30());
      addRegUsage_PPC32AMode(u, i->Pin.AvLdSt.addr);
      return;
   case Pin_AvUnary:
      addHRegUse(u, HRmWrite, i->Pin.AvUnary.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvUnary.src);
      return;
   case Pin_AvBinary:
      addHRegUse(u, HRmWrite, i->Pin.AvBinary.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvBinary.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvBinary.srcR);
      return;
   case Pin_AvBin8x16:
      addHRegUse(u, HRmWrite, i->Pin.AvBin8x16.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvBin8x16.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvBin8x16.srcR);
      return;
   case Pin_AvBin16x8:
      addHRegUse(u, HRmWrite, i->Pin.AvBin16x8.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvBin16x8.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvBin16x8.srcR);
      return;
   case Pin_AvBin32x4:
      addHRegUse(u, HRmWrite, i->Pin.AvBin32x4.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvBin32x4.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvBin32x4.srcR);
      if (i->Pin.AvBin32x4.op == Pav_MULF)
         addHRegUse(u, HRmWrite, hregPPC32_GPR29());
      return;
   case Pin_AvBin32Fx4:
      addHRegUse(u, HRmWrite, i->Pin.AvBin32Fx4.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvBin32Fx4.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvBin32Fx4.srcR);
      return;
   case Pin_AvPerm:
      addHRegUse(u, HRmWrite, i->Pin.AvPerm.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvPerm.ctl);
      addHRegUse(u, HRmRead,  i->Pin.AvPerm.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvPerm.srcR);
      return;
   case Pin_AvSel:
      addHRegUse(u, HRmWrite, i->Pin.AvSel.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvSel.ctl);
      addHRegUse(u, HRmRead,  i->Pin.AvSel.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvSel.srcR);
      return;
   case Pin_AvShlDbl:
      addHRegUse(u, HRmWrite, i->Pin.AvShlDbl.dst);
      addHRegUse(u, HRmRead,  i->Pin.AvShlDbl.srcL);
      addHRegUse(u, HRmRead,  i->Pin.AvShlDbl.srcR);
      return;
   case Pin_AvSplat:
      addHRegUse(u, HRmWrite, i->Pin.AvSplat.dst);
      addRegUsage_PPC32RI(u, i->Pin.AvSplat.src);