hdefs.c

unix下调试内存泄露的工具源代码

/*---------------------------------------------------------------*/
/*---                                                         ---*/
/*--- This file (host-ppc32/hdefs.c) is                       ---*/
/*--- Copyright (C) OpenWorks LLP.  All rights reserved.      ---*/
/*---                                                         ---*/
/*---------------------------------------------------------------*/

/*
   This file is part of LibVEX, a library for dynamic binary
   instrumentation and translation.

   Copyright (C) 2004-2005 OpenWorks LLP.  All rights reserved.

   This library is made available under a dual licensing scheme.

   If you link LibVEX against other code all of which is itself
   licensed under the GNU General Public License, version 2 dated June
   1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL
   v2, as appearing in the file LICENSE.GPL.  If the file LICENSE.GPL
   is missing, you can obtain a copy of the GPL v2 from the Free
   Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA
   02110-1301, USA.

   For any other uses of LibVEX, you must first obtain a commercial
   license from OpenWorks LLP.  Please contact [e-mail]
   for information about commercial licensing.

   This software is provided by OpenWorks LLP "as is" and any express
   or implied warranties, including, but not limited to, the implied
   warranties of merchantability and fitness for a particular purpose
   are disclaimed.  In no event shall OpenWorks LLP be liable for any
   direct, indirect, incidental, special, exemplary, or consequential
   damages (including, but not limited to, procurement of substitute
   goods or services; loss of use, data, or profits; or business
   interruption) however caused and on any theory of liability,
   whether in contract, strict liability, or tort (including
   negligence or otherwise) arising in any way out of the use of this
   software, even if advised of the possibility of such damage.

   Neither the names of the U.S. Department of Energy nor the
   University of California nor the names of its contributors may be
   used to endorse or promote products derived from this software
   without prior written permission.
*/

#include "libvex_basictypes.h"
#include "libvex.h"
#include "libvex_trc_values.h"

#include "main/vex_util.h"
#include "host-generic/h_generic_regs.h"
#include "host-ppc32/hdefs.h"


/* --------- Registers. --------- */

void ppHRegPPC32 ( HReg reg ) 
{
   Int r;
   static HChar* ireg32_names[32] 
      = { "%r0",  "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
          "%r8",  "%r9",  "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
          "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
          "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31" };
   /* Be generic for all virtual regs. */
   if (hregIsVirtual(reg)) {
      ppHReg(reg);
      return;
   }
   /* But specific for real regs. */
   switch (hregClass(reg)) {
   case HRcInt32:
      r = hregNumber(reg);
      vassert(r >= 0 && r < 32);
      vex_printf("%s", ireg32_names[r]);
      return;
   case HRcFlt64:
      r = hregNumber(reg);
      vassert(r >= 0 && r < 32);
      vex_printf("%%fr%d", r);
      return;
   case HRcVec128:
      r = hregNumber(reg);
      vassert(r >= 0 && r < 32);
      vex_printf("%%v%d", r);
      return;
   default:
      vpanic("ppHRegPPC32");
   }
}

HReg hregPPC32_GPR0  ( void ) { return mkHReg( 0, HRcInt32, False); }
HReg hregPPC32_GPR1  ( void ) { return mkHReg( 1, HRcInt32, False); }
HReg hregPPC32_GPR2  ( void ) { return mkHReg( 2, HRcInt32, False); }
HReg hregPPC32_GPR3  ( void ) { return mkHReg( 3, HRcInt32, False); }
HReg hregPPC32_GPR4  ( void ) { return mkHReg( 4, HRcInt32, False); }
HReg hregPPC32_GPR5  ( void ) { return mkHReg( 5, HRcInt32, False); }
HReg hregPPC32_GPR6  ( void ) { return mkHReg( 6, HRcInt32, False); }
HReg hregPPC32_GPR7  ( void ) { return mkHReg( 7, HRcInt32, False); }
HReg hregPPC32_GPR8  ( void ) { return mkHReg( 8, HRcInt32, False); }
HReg hregPPC32_GPR9  ( void ) { return mkHReg( 9, HRcInt32, False); }
HReg hregPPC32_GPR10 ( void ) { return mkHReg(10, HRcInt32, False); }
HReg hregPPC32_GPR11 ( void ) { return mkHReg(11, HRcInt32, False); }
HReg hregPPC32_GPR12 ( void ) { return mkHReg(12, HRcInt32, False); }
HReg hregPPC32_GPR13 ( void ) { return mkHReg(13, HRcInt32, False); }
HReg hregPPC32_GPR14 ( void ) { return mkHReg(14, HRcInt32, False); }
HReg hregPPC32_GPR15 ( void ) { return mkHReg(15, HRcInt32, False); }
HReg hregPPC32_GPR16 ( void ) { return mkHReg(16, HRcInt32, False); }
HReg hregPPC32_GPR17 ( void ) { return mkHReg(17, HRcInt32, False); }
HReg hregPPC32_GPR18 ( void ) { return mkHReg(18, HRcInt32, False); }
HReg hregPPC32_GPR19 ( void ) { return mkHReg(19, HRcInt32, False); }
HReg hregPPC32_GPR20 ( void ) { return mkHReg(20, HRcInt32, False); }
HReg hregPPC32_GPR21 ( void ) { return mkHReg(21, HRcInt32, False); }
HReg hregPPC32_GPR22 ( void ) { return mkHReg(22, HRcInt32, False); }
HReg hregPPC32_GPR23 ( void ) { return mkHReg(23, HRcInt32, False); }
HReg hregPPC32_GPR24 ( void ) { return mkHReg(24, HRcInt32, False); }
HReg hregPPC32_GPR25 ( void ) { return mkHReg(25, HRcInt32, False); }
HReg hregPPC32_GPR26 ( void ) { return mkHReg(26, HRcInt32, False); }
HReg hregPPC32_GPR27 ( void ) { return mkHReg(27, HRcInt32, False); }
HReg hregPPC32_GPR28 ( void ) { return mkHReg(28, HRcInt32, False); }
HReg hregPPC32_GPR29 ( void ) { return mkHReg(29, HRcInt32, False); }
HReg hregPPC32_GPR30 ( void ) { return mkHReg(30, HRcInt32, False); }
HReg hregPPC32_GPR31 ( void ) { return mkHReg(31, HRcInt32, False); }

HReg hregPPC32_FPR0  ( void ) { return mkHReg( 0, HRcFlt64, False); }
HReg hregPPC32_FPR1  ( void ) { return mkHReg( 1, HRcFlt64, False); }
HReg hregPPC32_FPR2  ( void ) { return mkHReg( 2, HRcFlt64, False); }
HReg hregPPC32_FPR3  ( void ) { return mkHReg( 3, HRcFlt64, False); }
HReg hregPPC32_FPR4  ( void ) { return mkHReg( 4, HRcFlt64, False); }
HReg hregPPC32_FPR5  ( void ) { return mkHReg( 5, HRcFlt64, False); }
HReg hregPPC32_FPR6  ( void ) { return mkHReg( 6, HRcFlt64, False); }
HReg hregPPC32_FPR7  ( void ) { return mkHReg( 7, HRcFlt64, False); }
HReg hregPPC32_FPR8  ( void ) { return mkHReg( 8, HRcFlt64, False); }
HReg hregPPC32_FPR9  ( void ) { return mkHReg( 9, HRcFlt64, False); }
HReg hregPPC32_FPR10 ( void ) { return mkHReg(10, HRcFlt64, False); }
HReg hregPPC32_FPR11 ( void ) { return mkHReg(11, HRcFlt64, False); }
HReg hregPPC32_FPR12 ( void ) { return mkHReg(12, HRcFlt64, False); }
HReg hregPPC32_FPR13 ( void ) { return mkHReg(13, HRcFlt64, False); }
HReg hregPPC32_FPR14 ( void ) { return mkHReg(14, HRcFlt64, False); }
HReg hregPPC32_FPR15 ( void ) { return mkHReg(15, HRcFlt64, False); }
HReg hregPPC32_FPR16 ( void ) { return mkHReg(16, HRcFlt64, False); }
HReg hregPPC32_FPR17 ( void ) { return mkHReg(17, HRcFlt64, False); }
HReg hregPPC32_FPR18 ( void ) { return mkHReg(18, HRcFlt64, False); }
HReg hregPPC32_FPR19 ( void ) { return mkHReg(19, HRcFlt64, False); }
HReg hregPPC32_FPR20 ( void ) { return mkHReg(20, HRcFlt64, False); }
HReg hregPPC32_FPR21 ( void ) { return mkHReg(21, HRcFlt64, False); }
HReg hregPPC32_FPR22 ( void ) { return mkHReg(22, HRcFlt64, False); }
HReg hregPPC32_FPR23 ( void ) { return mkHReg(23, HRcFlt64, False); }
HReg hregPPC32_FPR24 ( void ) { return mkHReg(24, HRcFlt64, False); }
HReg hregPPC32_FPR25 ( void ) { return mkHReg(25, HRcFlt64, False); }
HReg hregPPC32_FPR26 ( void ) { return mkHReg(26, HRcFlt64, False); }
HReg hregPPC32_FPR27 ( void ) { return mkHReg(27, HRcFlt64, False); }
HReg hregPPC32_FPR28 ( void ) { return mkHReg(28, HRcFlt64, False); }
HReg hregPPC32_FPR29 ( void ) { return mkHReg(29, HRcFlt64, False); }
HReg hregPPC32_FPR30 ( void ) { return mkHReg(30, HRcFlt64, False); }
HReg hregPPC32_FPR31 ( void ) { return mkHReg(31, HRcFlt64, False); }

HReg hregPPC32_VR0  ( void ) { return mkHReg( 0, HRcVec128, False); }
HReg hregPPC32_VR1  ( void ) { return mkHReg( 1, HRcVec128, False); }
HReg hregPPC32_VR2  ( void ) { return mkHReg( 2, HRcVec128, False); }
HReg hregPPC32_VR3  ( void ) { return mkHReg( 3, HRcVec128, False); }
HReg hregPPC32_VR4  ( void ) { return mkHReg( 4, HRcVec128, False); }
HReg hregPPC32_VR5  ( void ) { return mkHReg( 5, HRcVec128, False); }
HReg hregPPC32_VR6  ( void ) { return mkHReg( 6, HRcVec128, False); }
HReg hregPPC32_VR7  ( void ) { return mkHReg( 7, HRcVec128, False); }
HReg hregPPC32_VR8  ( void ) { return mkHReg( 8, HRcVec128, False); }
HReg hregPPC32_VR9  ( void ) { return mkHReg( 9, HRcVec128, False); }
HReg hregPPC32_VR10 ( void ) { return mkHReg(10, HRcVec128, False); }
HReg hregPPC32_VR11 ( void ) { return mkHReg(11, HRcVec128, False); }
HReg hregPPC32_VR12 ( void ) { return mkHReg(12, HRcVec128, False); }
HReg hregPPC32_VR13 ( void ) { return mkHReg(13, HRcVec128, False); }
HReg hregPPC32_VR14 ( void ) { return mkHReg(14, HRcVec128, False); }
HReg hregPPC32_VR15 ( void ) { return mkHReg(15, HRcVec128, False); }
HReg hregPPC32_VR16 ( void ) { return mkHReg(16, HRcVec128, False); }
HReg hregPPC32_VR17 ( void ) { return mkHReg(17, HRcVec128, False); }
HReg hregPPC32_VR18 ( void ) { return mkHReg(18, HRcVec128, False); }
HReg hregPPC32_VR19 ( void ) { return mkHReg(19, HRcVec128, False); }
HReg hregPPC32_VR20 ( void ) { return mkHReg(20, HRcVec128, False); }
HReg hregPPC32_VR21 ( void ) { return mkHReg(21, HRcVec128, False); }
HReg hregPPC32_VR22 ( void ) { return mkHReg(22, HRcVec128, False); }
HReg hregPPC32_VR23 ( void ) { return mkHReg(23, HRcVec128, False); }
HReg hregPPC32_VR24 ( void ) { return mkHReg(24, HRcVec128, False); }
HReg hregPPC32_VR25 ( void ) { return mkHReg(25, HRcVec128, False); }
HReg hregPPC32_VR26 ( void ) { return mkHReg(26, HRcVec128, False); }
HReg hregPPC32_VR27 ( void ) { return mkHReg(27, HRcVec128, False); }
HReg hregPPC32_VR28 ( void ) { return mkHReg(28, HRcVec128, False); }
HReg hregPPC32_VR29 ( void ) { return mkHReg(29, HRcVec128, False); }
HReg hregPPC32_VR30 ( void ) { return mkHReg(30, HRcVec128, False); }
HReg hregPPC32_VR31 ( void ) { return mkHReg(31, HRcVec128, False); }

void getAllocableRegs_PPC32 ( Int* nregs, HReg** arr )
{
   UInt i=0;
   *nregs = 90 - 24 - 24;
   *arr = LibVEX_Alloc(*nregs * sizeof(HReg));
   // GPR0 = scratch reg where possible - some ops interpret as value zero
   // GPR1 = stack pointer
   // GPR2 = TOC pointer
   (*arr)[i++] = hregPPC32_GPR3();
   (*arr)[i++] = hregPPC32_GPR4();
   (*arr)[i++] = hregPPC32_GPR5();
   (*arr)[i++] = hregPPC32_GPR6();
   (*arr)[i++] = hregPPC32_GPR7();
   (*arr)[i++] = hregPPC32_GPR8();
   (*arr)[i++] = hregPPC32_GPR9();
   (*arr)[i++] = hregPPC32_GPR10();
   (*arr)[i++] = hregPPC32_GPR11();
   (*arr)[i++] = hregPPC32_GPR12();
   // GPR13 = thread specific pointer
   (*arr)[i++] = hregPPC32_GPR14();
   (*arr)[i++] = hregPPC32_GPR15();
   (*arr)[i++] = hregPPC32_GPR16();
   (*arr)[i++] = hregPPC32_GPR17();
   (*arr)[i++] = hregPPC32_GPR18();
   (*arr)[i++] = hregPPC32_GPR19();
   (*arr)[i++] = hregPPC32_GPR20();
   (*arr)[i++] = hregPPC32_GPR21();
   (*arr)[i++] = hregPPC32_GPR22();
   (*arr)[i++] = hregPPC32_GPR23();
   (*arr)[i++] = hregPPC32_GPR24();
   (*arr)[i++] = hregPPC32_GPR25();
   (*arr)[i++] = hregPPC32_GPR26();
   (*arr)[i++] = hregPPC32_GPR27();
   (*arr)[i++] = hregPPC32_GPR28();
   (*arr)[i++] = hregPPC32_GPR29();
   // GPR30 AltiVec spill reg temporary
   // GPR31 = GuestStatePtr

   (*arr)[i++] = hregPPC32_FPR0();
   (*arr)[i++] = hregPPC32_FPR1();
   (*arr)[i++] = hregPPC32_FPR2();
   (*arr)[i++] = hregPPC32_FPR3();
   (*arr)[i++] = hregPPC32_FPR4();
   (*arr)[i++] = hregPPC32_FPR5();
   (*arr)[i++] = hregPPC32_FPR6();
   (*arr)[i++] = hregPPC32_FPR7();
/*
   (*arr)[i++] = hregPPC32_FPR8();
   (*arr)[i++] = hregPPC32_FPR9();
   (*arr)[i++] = hregPPC32_FPR10();
   (*arr)[i++] = hregPPC32_FPR11();
   (*arr)[i++] = hregPPC32_FPR12();
   (*arr)[i++] = hregPPC32_FPR13();
   (*arr)[i++] = hregPPC32_FPR14();
   (*arr)[i++] = hregPPC32_FPR15();
   (*arr)[i++] = hregPPC32_FPR16();
   (*arr)[i++] = hregPPC32_FPR17();
   (*arr)[i++] = hregPPC32_FPR18();
   (*arr)[i++] = hregPPC32_FPR19();
   (*arr)[i++] = hregPPC32_FPR20();
   (*arr)[i++] = hregPPC32_FPR21();
   (*arr)[i++] = hregPPC32_FPR22();
   (*arr)[i++] = hregPPC32_FPR23();
   (*arr)[i++] = hregPPC32_FPR24();
   (*arr)[i++] = hregPPC32_FPR25();
   (*arr)[i++] = hregPPC32_FPR26();
   (*arr)[i++] = hregPPC32_FPR27();
   (*arr)[i++] = hregPPC32_FPR28();
   (*arr)[i++] = hregPPC32_FPR29();
   (*arr)[i++] = hregPPC32_FPR30();
   (*arr)[i++] = hregPPC32_FPR31();
*/
   (*arr)[i++] = hregPPC32_VR0();
   (*arr)[i++] = hregPPC32_VR1();
   (*arr)[i++] = hregPPC32_VR2();
   (*arr)[i++] = hregPPC32_VR3();
   (*arr)[i++] = hregPPC32_VR4();
   (*arr)[i++] = hregPPC32_VR5();
   (*arr)[i++] = hregPPC32_VR6();
   (*arr)[i++] = hregPPC32_VR7();
/*
   (*arr)[i++] = hregPPC32_VR8();
   (*arr)[i++] = hregPPC32_VR9();
   (*arr)[i++] = hregPPC32_VR10();
   (*arr)[i++] = hregPPC32_VR11();
   (*arr)[i++] = hregPPC32_VR12();
   (*arr)[i++] = hregPPC32_VR13();
   (*arr)[i++] = hregPPC32_VR14();
   (*arr)[i++] = hregPPC32_VR15();
   (*arr)[i++] = hregPPC32_VR16();
   (*arr)[i++] = hregPPC32_VR17();
   (*arr)[i++] = hregPPC32_VR18();
   (*arr)[i++] = hregPPC32_VR19();
   (*arr)[i++] = hregPPC32_VR20();
   (*arr)[i++] = hregPPC32_VR21();
   (*arr)[i++] = hregPPC32_VR22();
   (*arr)[i++] = hregPPC32_VR23();
   (*arr)[i++] = hregPPC32_VR24();
   (*arr)[i++] = hregPPC32_VR25();
   (*arr)[i++] = hregPPC32_VR26();
   (*arr)[i++] = hregPPC32_VR27();
   (*arr)[i++] = hregPPC32_VR28();
   (*arr)[i++] = hregPPC32_VR29();
   (*arr)[i++] = hregPPC32_VR30();
   (*arr)[i++] = hregPPC32_VR31();
*/
   vassert(i == *nregs);
}


/* --------- Condition codes, Intel encoding. --------- */

HChar* showPPC32CondCode ( PPC32CondCode cond )
{
   if (cond.test == Pct_ALWAYS) return "always";

   switch (cond.flag) {
      case Pcf_7SO: return (cond.test == Pct_TRUE) ? "cr7.so=1" : "cr7.so=0";
      case Pcf_7EQ: return (cond.test == Pct_TRUE) ? "cr7.eq=1" : "cr7.eq=0";
      case Pcf_7GT: return (cond.test == Pct_TRUE) ? "cr7.gt=1" : "cr7.gt=0";
      case Pcf_7LT: return (cond.test == Pct_TRUE) ? "cr7.lt=1" : "cr7.lt=0";
      default: vpanic("ppPPC32CondCode");
   }
}

/* construct condition code */
PPC32CondCode mk_PPCCondCode ( PPC32CondTest test, PPC32CondFlag flag )
{
   PPC32CondCode cc;
   cc.flag = flag;
   cc.test = test;
   return cc;
}

/* false->true, true->false */
PPC32CondTest invertCondTest ( PPC32CondTest ct )
{
   vassert(ct != Pct_ALWAYS);
   return (ct == Pct_TRUE) ? Pct_FALSE : Pct_TRUE;
}


/* --------- PPCAMode: memory address expressions. --------- */

PPC32AMode* PPC32AMode_IR ( Int idx, HReg base ) {
   PPC32AMode* am = LibVEX_Alloc(sizeof(PPC32AMode));
   vassert(idx >= -0x8000 && idx < 0x8000);
   am->tag = Pam_IR;
   am->Pam.IR.base = base;
   am->Pam.IR.index = idx;
   return am;
}
PPC32AMode* PPC32AMode_RR ( HReg idx, HReg base ) {
   PPC32AMode* am = LibVEX_Alloc(sizeof(PPC32AMode));
   am->tag = Pam_RR;
   am->Pam.RR.base = base;
   am->Pam.RR.index = idx;
   return am;
}

PPC32AMode* dopyPPC32AMode ( PPC32AMode* am ) {
   switch (am->tag) {
   case Pam_IR: 
      return PPC32AMode_IR( am->Pam.IR.index, am->Pam.IR.base );
   case Pam_RR: 
      return PPC32AMode_RR( am->Pam.RR.index, am->Pam.RR.base );
   default:
      vpanic("dopyPPC32AMode");
   }
}

void ppPPC32AMode ( PPC32AMode* am ) {
   switch (am->tag) {
   case Pam_IR: 
      if (am->Pam.IR.index == 0)
         vex_printf("0(");
      else
         vex_printf("%d(", (Int)am->Pam.IR.index);
      ppHRegPPC32(am->Pam.IR.base);
      vex_printf(")");
      return;
   case Pam_RR:
      ppHRegPPC32(am->Pam.RR.base);
      vex_printf(",");
      ppHRegPPC32(am->Pam.RR.index);
      return;
   default:
      vpanic("ppPPC32AMode");
   }
}

static void addRegUsage_PPC32AMode ( HRegUsage* u, PPC32AMode* am ) {
   switch (am->tag) {
   case Pam_IR: 
      addHRegUse(u, HRmRead, am->Pam.IR.base);
      return;
   case Pam_RR:
      addHRegUse(u, HRmRead, am->Pam.RR.base);
      addHRegUse(u, HRmRead, am->Pam.RR.index);
      return;
   default:
      vpanic("addRegUsage_PPC32AMode");
   }
}

static void mapRegs_PPC32AMode ( HRegRemap* m, PPC32AMode* am ) {