hdefs.h

unix下调试内存泄露的工具源代码

      Pav_PACKUUM, Pav_PACKUUS, Pav_PACKSUS, Pav_PACKSSS,
      Pav_PACKPXL,

      /* Merge */
      Pav_MRGHI, Pav_MRGLO,

      /* Floating point binary */
      Pav_ADDF, Pav_SUBF, Pav_MULF,
      Pav_MAXF, Pav_MINF,
      Pav_CMPEQF, Pav_CMPGTF, Pav_CMPGEF,

//..       /* Floating point unary */
//..       Xsse_RCPF, Xsse_RSQRTF, Xsse_SQRTF,
   }
   PPC32AvOp;

extern HChar* showPPC32AvOp ( PPC32AvOp );


/* --------- */
typedef
   enum {
      Pin_LI32,       /* load 32-bit immediate (fake insn) */
      Pin_Alu32,      /* 32-bit add/sub/and/or/xor/shl/shr/sar */
      Pin_Cmp32,      /* 32-bit compare */
      Pin_Unary32,    /* 32-bit not, neg, clz */
      Pin_MulL,       /* widening multiply */
      Pin_Div,        /* div */
      Pin_Call,       /* call to address in register */
      Pin_Goto,       /* conditional/unconditional jmp to dst */
      Pin_CMov32,     /* conditional move */
      Pin_Load,       /* load a 8|16|32 bit value from mem */
      Pin_Store,      /* store a 8|16|32 bit value to mem */
      Pin_Set32,      /* convert condition code to 32-bit value */
      Pin_MfCR,       /* move from condition register to GPR */
      Pin_MFence,     /* mem fence */

      Pin_FpUnary,    /* FP unary op */
      Pin_FpBinary,   /* FP binary op */
      Pin_FpLdSt,     /* FP load/store */
      Pin_FpF64toF32, /* FP round IEEE754 double to IEEE754 single */
      Pin_FpF64toI32, /* FP round IEEE754 double to 32-bit integer */
      Pin_FpCMov,     /* FP floating point conditional move */
      Pin_FpLdFPSCR,  /* mtfsf */
      Pin_FpCmp,      /* FP compare, generating value into int reg */
      Pin_RdWrLR,     /* Read/Write Link Register */

//    Pin_AvConst,    /* Generate restricted AV literal */
      Pin_AvLdSt,     /* AV load/store (kludging for AMode_IR) */
      Pin_AvUnary,    /* AV unary general reg=>reg */

      Pin_AvBinary,   /* AV binary general reg,reg=>reg */
      Pin_AvBin8x16,  /* AV binary, 8x4 */
      Pin_AvBin16x8,  /* AV binary, 16x4 */
      Pin_AvBin32x4,  /* AV binary, 32x4 */

      Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */

      Pin_AvPerm,     /* AV permute (shuffle) */
      Pin_AvSel,      /* AV select */
      Pin_AvShlDbl,   /* AV shift-left double by imm */
      Pin_AvSplat,    /* One elem repeated throughout dst */
      Pin_AvLdVSCR,   /* mtvscr */
      Pin_AvCMov      /* AV conditional move */
   }
   PPC32InstrTag;

/* Destinations are on the LEFT (first operand) */

typedef
   struct {
      PPC32InstrTag tag;
      union {
         /* Get a 32-bit literal into a register.  May turn into one or
	    two real insns. */
         struct {
            HReg dst;
            UInt imm32;
         } LI32;
         /* Integer add/sub/and/or/xor/shl/shr/sar.  Limitations:
            - For add, the immediate, if it exists, is a signed 16.
            - For sub, the immediate, if it exists, is a signed 16
              which may not be -32768, since no such instruction 
              exists, and so we have to emit addi with +32768, but 
              that is not possible.
            - For and/or/xor,  the immediate, if it exists, 
              is an unsigned 16.
            - For shr/shr/sar, the immediate, if it exists,
              is a signed 5-bit value between 1 and 31 inclusive.
         */
         struct {
            PPC32AluOp op;
            HReg       dst;
            HReg       srcL;
            PPC32RH*   srcR;
         } Alu32;
         /* If signed, the immediate, if it exists, is a signed 16,
            else it is an unsigned 16. */
         struct {
            Bool     syned;
            UInt     crfD;
            HReg     srcL;
            PPC32RH* srcR;
         } Cmp32;
         /* Not and Neg */
         struct {
            PPC32UnaryOp op;
            HReg         dst;
            HReg         src;
         } Unary32;
         struct {
            Bool syned;  /* meaningless if hi32==False */
            Bool hi32;   /* False=>low, True=>high */
            HReg dst;
            HReg srcL;
            HReg srcR;
         } MulL;
         /* ppc32 div/divu instruction. */
         struct {
            Bool syned;
            HReg dst;
            HReg srcL;
            HReg srcR;
         } Div;
         /* Pseudo-insn.  Call target (an absolute address), on given
            condition (which could be Pct_ALWAYS). */
         struct {
            PPC32CondCode cond;
            Addr32        target;
            Int           regparms; /* 0 .. 9 */
         } Call;
         /* Pseudo-insn.  Goto dst, on given condition (which could be
            Pct_ALWAYS). */
         struct {
            IRJumpKind    jk;
            PPC32CondCode cond;
            PPC32RI*      dst;
         } Goto;
         /* Mov src to dst on the given condition, which may not
            be the bogus Pct_ALWAYS. */
         struct {
            PPC32CondCode cond;
            HReg          dst;
            PPC32RI*      src;
         } CMov32;
         /* Sign/Zero extending loads.  Dst size is always 32 bits. */
         struct {
            UChar       sz; /* 1|2|4 */
            Bool        syned;
            HReg        dst;
            PPC32AMode* src;
         } Load;
         /* 32/16/8 bit stores */
         struct {
            UChar       sz; /* 1|2|4 */
            PPC32AMode* dst;
            HReg        src;
         } Store;
         /* Convert a ppc32 condition code to a 32-bit value (0 or 1). */
         struct {
            PPC32CondCode cond;
            HReg          dst;
         } Set32;
         /* Move the entire CR to a GPR */
         struct {
            HReg dst;
         } MfCR;
         /* Mem fence.  In short, an insn which flushes all preceding
            loads and stores as much as possible before continuing.
            On PPC32 we emit a "sync". */
         struct {
         } MFence;

         /* PPC32 Floating point */
         struct {
            PPC32FpOp op;
            HReg      dst;
            HReg      src;
         } FpUnary;
         struct {
            PPC32FpOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } FpBinary;
         struct {
            Bool        isLoad;
            UChar       sz; /* only 4 (IEEE single) or 8 (IEEE double) */
            HReg        reg;
            PPC32AMode* addr;
         } FpLdSt;
         /* By observing the current FPU rounding mode, round src into dst,
            re-interpreting dst to an IEEE754 32-bit (float) type. */
         struct {
            HReg src;
            HReg dst;
         } FpF64toF32;
         /* By observing the current FPU rounding mode, round src into dst,
            re-interpreting dst to an 32-bit integer type. */
         struct {
            HReg src;
            HReg dst;
         } FpF64toI32;
         /* Mov src to dst on the given condition, which may not
            be the bogus Xcc_ALWAYS. */
         struct {
            PPC32CondCode cond;
            HReg          dst;
            HReg          src;
         } FpCMov;
         /* Load FP Status & Control Register */
         struct {
            HReg src;
         } FpLdFPSCR;
         /* Do a compare, generating result into an int register. */
         struct {
            UChar crfD;
            HReg  dst;
            HReg  srcL;
            HReg  srcR;
         } FpCmp;

         /* Read/Write Link Register */
         struct {
            Bool wrLR;
            HReg gpr;
         } RdWrLR;

         /* Simplistic AltiVec */
         struct {
            Bool        isLoad;
            UChar       sz;      /* 8|16|32|128 */
            HReg        reg;
            PPC32AMode* addr;
         } AvLdSt;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      src;
         } AvUnary;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } AvBinary;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } AvBin8x16;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } AvBin16x8;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } AvBin32x4;
         struct {
            PPC32AvOp op;
            HReg      dst;
            HReg      srcL;
            HReg      srcR;
         } AvBin32Fx4;
         /* Perm,Sel,SlDbl,Splat are all weird AV permutations */
         struct {
            HReg ctl;
            HReg dst;
            HReg srcL;
            HReg srcR;
         } AvPerm;
         struct {
            HReg ctl;
            HReg dst;
            HReg srcL;
            HReg srcR;
         } AvSel;
         struct {
            UChar shift;
            HReg  dst;
            HReg  srcL;
            HReg  srcR;
         } AvShlDbl;
         struct {
            UChar    sz;   /* 8,16,32 */
            HReg     dst;
            PPC32RI* src;
         } AvSplat;
         /* Mov src to dst on the given condition, which may not
            be the bogus Xcc_ALWAYS. */
         struct {
            PPC32CondCode cond;
            HReg          dst;
            HReg          src;
         } AvCMov;
         /* Load AltiVec Status & Control Register */
         struct {
            HReg src;
         } AvLdVSCR;
       } Pin;
   }
   PPC32Instr;


extern PPC32Instr* PPC32Instr_LI32       ( HReg, UInt );
extern PPC32Instr* PPC32Instr_Alu32      ( PPC32AluOp, HReg, HReg, PPC32RH* );
extern PPC32Instr* PPC32Instr_Cmp32      ( Bool,       UInt, HReg, PPC32RH* );
extern PPC32Instr* PPC32Instr_Unary32    ( PPC32UnaryOp op, HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_MulL       ( Bool syned, Bool hi32, HReg, HReg, HReg );
extern PPC32Instr* PPC32Instr_Div        ( Bool syned, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_Call       ( PPC32CondCode, Addr32, Int );
extern PPC32Instr* PPC32Instr_Goto       ( IRJumpKind, PPC32CondCode cond, PPC32RI* dst );
extern PPC32Instr* PPC32Instr_CMov32     ( PPC32CondCode, HReg dst, PPC32RI* src );
extern PPC32Instr* PPC32Instr_Load       ( UChar sz, Bool syned,
                                           HReg dst, PPC32AMode* src );
extern PPC32Instr* PPC32Instr_Store      ( UChar sz, PPC32AMode* dst, HReg src );
extern PPC32Instr* PPC32Instr_Set32      ( PPC32CondCode cond, HReg dst );
extern PPC32Instr* PPC32Instr_MfCR       ( HReg dst );
extern PPC32Instr* PPC32Instr_MFence     ( void );

extern PPC32Instr* PPC32Instr_FpUnary    ( PPC32FpOp op, HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_FpBinary   ( PPC32FpOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_FpLdSt     ( Bool isLoad, UChar sz, HReg, PPC32AMode* );
extern PPC32Instr* PPC32Instr_FpF64toF32 ( HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_FpF64toI32 ( HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_FpCMov     ( PPC32CondCode, HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_FpLdFPSCR  ( HReg src );
extern PPC32Instr* PPC32Instr_FpCmp      ( HReg dst, HReg srcL, HReg srcR );

extern PPC32Instr* PPC32Instr_RdWrLR     ( Bool wrLR, HReg gpr );

extern PPC32Instr* PPC32Instr_AvLdSt     ( Bool isLoad, UChar sz, HReg, PPC32AMode* );
extern PPC32Instr* PPC32Instr_AvUnary    ( PPC32AvOp op, HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_AvBinary   ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin8x16  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin16x8  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32x4  ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvBin32Fx4 ( PPC32AvOp op, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvPerm     ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvSel      ( HReg ctl, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvShlDbl   ( UChar shift, HReg dst, HReg srcL, HReg srcR );
extern PPC32Instr* PPC32Instr_AvSplat    ( UChar sz, HReg dst, PPC32RI* src );
extern PPC32Instr* PPC32Instr_AvCMov     ( PPC32CondCode, HReg dst, HReg src );
extern PPC32Instr* PPC32Instr_AvLdVSCR   ( HReg src );

extern void ppPPC32Instr ( PPC32Instr* );

/* Some functions that insulate the register allocator from details
   of the underlying instruction set. */
extern void         getRegUsage_PPC32Instr ( HRegUsage*, PPC32Instr* );
extern void         mapRegs_PPC32Instr     ( HRegRemap*, PPC32Instr* );
extern Bool         isMove_PPC32Instr      ( PPC32Instr*, HReg*, HReg* );
extern Int          emit_PPC32Instr        ( UChar* buf, Int nbuf, PPC32Instr* );
extern PPC32Instr*  genSpill_PPC32         ( HReg rreg, UShort offsetB );
extern PPC32Instr*  genReload_PPC32        ( HReg rreg, UShort offsetB );
extern void         getAllocableRegs_PPC32 ( Int*, HReg** );
extern HInstrArray* iselBB_PPC32           ( IRBB*, VexArchInfo* );

#endif /* ndef __LIBVEX_HOST_PPC32_HDEFS_H */

/*---------------------------------------------------------------*/
/*--- end                                  host-ppc32/hdefs.h ---*/
/*---------------------------------------------------------------*/