hdefs.c

unix下调试内存泄露的工具源代码

}

ARMAMode3* dopyARMAMode3 ( ARMAMode3* am ) {
   switch (am->tag) {
   case ARMam3_RI:
       return ARMAMode3_RI( am->ARMam3.RI.Rn, am->ARMam3.RI.imm );
   case ARMam3_RR:
       return ARMAMode3_RR( am->ARMam3.RR.Rn, am->ARMam3.RR.Rm );
   default:
       vpanic("dopyARMAMode3");
   }
}

void ppARMAMode3 ( ARMAMode3* am ) {
   switch (am->tag) {
   case ARMam3_RI:
   case ARMam3_RR:
       vex_printf("ppARMAMode3: Not implemented");
       break;
   default:
       vpanic("ppARMAMode3");
   }
}

/*
static void addRegUsage_ARMAMode1 ( HRegUsage* u, ARMAMode2* am ) {
static void mapRegs_ARMAMode2 ( HRegRemap* m, ARMAMode2* am ) {
*/

/* ------ Branch destination ------ */

ARMBranchDest* ARMBranchDest_Imm ( ARMImm24 imm24 ) {
   ARMBranchDest* branch_dest = LibVEX_Alloc(sizeof(ARMBranchDest));
   branch_dest->tag = ARMbdImm;
   branch_dest->ARMbd.Imm.imm24 = imm24;
   return branch_dest;
}
ARMBranchDest* ARMBranchDest_Reg ( HReg reg ) {
   ARMBranchDest* branch_dest = LibVEX_Alloc(sizeof(ARMBranchDest));
   branch_dest->tag = ARMbdReg;
   branch_dest->ARMbd.Reg.reg = reg;
   return branch_dest;
}

void ppARMBranchDest ( ARMBranchDest* branch_dest ) {
    switch (branch_dest->tag) {
    case ARMbdImm:
    case ARMbdReg:
       vex_printf("ppARMBranchDest: Not implemented");
       break;
    default:
	vpanic("ppX86RM");
    }
}




/* --------- Instructions. --------- */

HChar* showARMAluOp ( ARMAluOp op ) {
    switch (op) {
    case ARMalu_AND:  return "and";
    case ARMalu_ORR:  return "orr";
    case ARMalu_EOR:  return "eor";
    case ARMalu_SUB:  return "sub";
    case ARMalu_RSB:  return "rsb";
    case ARMalu_ADD:  return "add";
    case ARMalu_ADC:  return "adc";
    case ARMalu_SBC:  return "sbc";
    case ARMalu_RSC:  return "rsc";
    case ARMalu_TST:  return "tst";
    case ARMalu_TEQ:  return "teq";
    case ARMalu_CMP:  return "cmp";
    case ARMalu_CMN:  return "cmn";
    case ARMalu_MOV:  return "mov";
    case ARMalu_MVN:  return "mvn";
    case ARMalu_BIC:  return "bic";
    default: vpanic("showARMAluOp");
    }
}

/* --- Addressing Mode 1 --- */
ARMInstr* ARMInstr_DPCmp ( ARMAluOp op, HReg Rn,
			   ARMAMode1* shifter_op ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_DPCmp;
    i->ARMin.DPCmp.op = op;
    i->ARMin.DPCmp.Rn = Rn;
    i->ARMin.DPCmp.shifter_op = shifter_op;
    return i;
}

ARMInstr* ARMInstr_DPInstr1 ( ARMAluOp op, HReg Rd,
			      ARMAMode1* shifter_op ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_DPInstr1;
    i->ARMin.DPInstr1.op = op;
    i->ARMin.DPInstr1.Rd = Rd;
    i->ARMin.DPInstr1.shifter_op = shifter_op;
    return i;
}

ARMInstr* ARMInstr_DPInstr2 ( ARMAluOp op, HReg Rd, HReg Rn,
			      ARMAMode1* shifter_op ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_DPInstr2;
    i->ARMin.DPInstr2.op = op;
    i->ARMin.DPInstr2.Rd = Rd;
    i->ARMin.DPInstr2.Rn = Rn;
    i->ARMin.DPInstr2.shifter_op = shifter_op;
    return i;
}

/* --- Addressing Mode 2 --- */
ARMInstr* ARMInstr_LoadUB ( HReg Rd, ARMAMode2* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_LoadUB;
    i->ARMin.LoadUB.Rd = Rd;
    i->ARMin.LoadUB.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_StoreB ( HReg Rd, ARMAMode2* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_StoreB;
    i->ARMin.StoreB.Rd = Rd;
    i->ARMin.StoreB.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_LoadW ( HReg Rd, ARMAMode2* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_LoadW;
    i->ARMin.LoadW.Rd = Rd;
    i->ARMin.LoadW.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_StoreW ( HReg Rd, ARMAMode2* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_StoreW;
    i->ARMin.StoreW.Rd = Rd;
    i->ARMin.StoreW.addr_mode = addr_mode;
    return i;
}

/* --- Addressing Mode 3 --- */
ARMInstr* ARMInstr_LoadSB ( HReg Rd, ARMAMode3* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_LoadSB;
    i->ARMin.LoadSB.Rd = Rd;
    i->ARMin.LoadSB.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_LoadUH ( HReg Rd, ARMAMode3* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_LoadUH;
    i->ARMin.LoadUH.Rd = Rd;
    i->ARMin.LoadUH.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_LoadSH ( HReg Rd, ARMAMode3* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_LoadSH;
    i->ARMin.LoadSH.Rd = Rd;
    i->ARMin.LoadSH.addr_mode = addr_mode;
    return i;
}

ARMInstr* ARMInstr_StoreH ( HReg Rd, ARMAMode3* addr_mode ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_StoreH;
    i->ARMin.StoreH.Rd = Rd;
    i->ARMin.StoreH.addr_mode = addr_mode;
    return i;
}

/* --- Branch --- */
ARMInstr* ARMInstr_Branch ( ARMCondCode cond, ARMBranchDest* dest ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_Branch;
    i->ARMin.Branch.cond = cond;
    i->ARMin.Branch.dest = dest;
    return i;
}

ARMInstr* ARMInstr_BranchL ( ARMCondCode cond, ARMBranchDest* dest ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_BranchL;
    i->ARMin.BranchL.dest = dest;
    return i;
}

/* --- Literal --- */
ARMInstr* ARMInstr_Literal ( HReg reg, UInt imm ) {
    ARMInstr* i       = LibVEX_Alloc(sizeof(ARMInstr));
    i->tag = ARMin_Literal;
    i->ARMin.Literal.reg = reg;
    i->ARMin.Literal.imm = imm;
    return i;
}


void ppARMInstr ( ARMInstr* i ) {
    switch (i->tag) {
    case ARMin_DPCmp:
    case ARMin_DPInstr1:
    case ARMin_DPInstr2:
    case ARMin_LoadUB:
    case ARMin_StoreB:
    case ARMin_LoadW:
    case ARMin_StoreW:
    case ARMin_LoadSB:
    case ARMin_LoadUH:
    case ARMin_LoadSH:
    case ARMin_StoreH:
    case ARMin_Branch:
    case ARMin_BranchL:
    case ARMin_Literal:
	vex_printf("ppARMInstr: Not implemented");
	break;

    default:
	vpanic("ppARMInstr");
    }
}




/* --------- Helpers for register allocation. --------- */

void getRegUsage_ARMInstr ( HRegUsage* u, ARMInstr* i ) {
//    Bool unary;
    initHRegUsage(u);
    switch (i->tag) {
    case ARMin_DPCmp:
    case ARMin_DPInstr1:
    case ARMin_DPInstr2:
    case ARMin_LoadUB:
    case ARMin_StoreB:
    case ARMin_LoadW:
    case ARMin_StoreW:
    case ARMin_LoadSB:
    case ARMin_LoadUH:
    case ARMin_LoadSH:
    case ARMin_StoreH:
    case ARMin_Branch:
    case ARMin_BranchL:
    case ARMin_Literal:

    default:
	ppARMInstr(i);
	vpanic("getRegUsage_ARMInstr");
    }
}


/* local helper */
#if 0
static void mapReg(HRegRemap* m, HReg* r) {
   *r = lookupHRegRemap(m, *r);
}
#endif

void mapRegs_ARMInstr ( HRegRemap* m, ARMInstr* i ) {
    switch (i->tag) {
    case ARMin_DPCmp:
    case ARMin_DPInstr1:
    case ARMin_DPInstr2:
    case ARMin_LoadUB:
    case ARMin_StoreB:
    case ARMin_LoadW:
    case ARMin_StoreW:
    case ARMin_LoadSB:
    case ARMin_LoadUH:
    case ARMin_LoadSH:
    case ARMin_StoreH:
    case ARMin_Branch:
    case ARMin_BranchL:
    case ARMin_Literal:

    default:
	ppARMInstr(i);
	vpanic("getRegUsage_ARMInstr");
    }
}

/* Figure out if i represents a reg-reg move, and if so assign the
   source and destination to *src and *dst.  If in doubt say No.  Used
   by the register allocator to do move coalescing. 
*/
Bool isMove_ARMInstr ( ARMInstr* i, HReg* src, HReg* dst ) {
    return False;  // No optimisations for now...
}


/* Generate x86 spill/reload instructions under the direction of the
   register allocator.  Note it's critical these don't write the
   condition codes. */

ARMInstr* genSpill_ARM ( HReg rreg, Int offsetB ) {
//   ARMAMode1* am;
   vassert(offsetB >= 0);
   vassert(!hregIsVirtual(rreg));

   switch (hregClass(rreg)) {

   default: 
       ppHRegClass(hregClass(rreg));
       vpanic("genSpill_ARM: unimplemented regclass");
   }
}

ARMInstr* genReload_ARM ( HReg rreg, Int offsetB ) {
//   ARMAMode1* am;
   vassert(offsetB >= 0);
   vassert(!hregIsVirtual(rreg));

   switch (hregClass(rreg)) {

   default: 
       ppHRegClass(hregClass(rreg));
       vpanic("genReload_ARM: unimplemented regclass");
   }
}


/* Emit an instruction into buf and return the number of bytes used.
   Note that buf is not the insn's final place, and therefore it is
   imperative to emit position-independent code. */

Int emit_ARMInstr ( UChar* buf, Int nbuf, ARMInstr* i ) {
//    UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc;
    
//    UInt   xtra;
    UChar* p = &buf[0];
//    UChar* ptmp;
    vassert(nbuf >= 32);

    switch (i->tag) {
    case ARMin_DPCmp:
    case ARMin_DPInstr1:
    case ARMin_DPInstr2:
    case ARMin_LoadUB:
    case ARMin_StoreB:
    case ARMin_LoadW:
    case ARMin_StoreW:
    case ARMin_LoadSB:
    case ARMin_LoadUH:
    case ARMin_LoadSH:
    case ARMin_StoreH:
    case ARMin_Branch:
    case ARMin_BranchL:
    case ARMin_Literal:
    default: 
	goto bad;
    }

 bad:
    ppARMInstr(i);
    vpanic("emit_ARMInstr");
    /*NOTREACHED*/
    
// done:
    vassert(p - &buf[0] <= 32);
    return p - &buf[0];
}


/*---------------------------------------------------------------*/
/*--- end                                    host-x86/hdefs.c ---*/
/*---------------------------------------------------------------*/