📄 main.c
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// Enable compare operation, 150MHz/64
//EvaRegs.T2CON.all=0x160A;
//Disable compare Trip,diable compare output,compare out put force low
//Enable T1,T2 PWM output for six independence PWM
EvaRegs.T2CON.all=0x0802;
//Enable capture 1,2,3 select timer 4,detects falling edge
//EvaRegs.CAPCON.all=0x30A8;
EvaRegs.CAPCON.all=0x30A8;//LC/040510
EvaRegs.T2CNT=0;
EvaRegs.T2PR=0x0F42;
//EvaRegs.T2CMPR=0x0493;
//Enable Capture 4,5,6 interrupt //and compare interrupt
//EvaRegs.EVAIMRB.bit.T2CINT=1;
//EvaRegs.EVAIFRB.bit.T2CINT=1;
EvaRegs.CAPFIFO.all=0x1000;//lc/040531
EvaRegs.EVAIMRC.all=0x0007;
//EvaRegs.EVAIMRC.bit.CAP1INT=1;
//EvaRegs.EVAIMRC.bit.CAP2INT=1;
//EvaRegs.EVAIMRC.bit.CAP3INT=1;
EvaRegs.EVAIFRC.all=0x0007;
//EvaRegs.EVAIFRC.bit.CAP1INT=1;
//EvaRegs.EVAIFRC.bit.CAP2INT=1;
//EvaRegs.EVAIFRC.bit.CAP3INT=1;
EvaRegs.EXTCON.all=0x0000;
//Disable compare Trip,diable compare output,compare out put force low
//EvbRegs.GPTCONB.all=0x0000;
// Enable Output Compare PWM ,t4 force low t3 active high
EvbRegs.GPTCONB.all=0x0044; // for test ywt/061208A
// timer3 continuous Up/Down Mode, Reload when counter is 0
// Disable timer, Disable timer compare operation,150MHz
//EvbRegs.T3CON.all=0x0800;
// Enable T3 CMP/PWM, for six independence PWM
EvbRegs.T3CON.all=0x0802;
//Enable full compare, load when T1CNT=0 or T1CNT=T1PR,
//Active control register reload when T1CNT=0 or T1CNT=T1PR.
EvbRegs.COMCONB.all=0xA600;
// 1.5us dead time, 150MHz/16, Dead-band timer period=14
EvbRegs.DBTCONB.all=0x0EF0;
EvbRegs.T3CNT=0;
EvbRegs.T3PR=0x0F42;
//EvbRegs.T3CMPR=0x0500;;
//EvbRegs.CMPR4=0x04DC;
//EvbRegs.CMPR5=0x05DC;
//EvbRegs.CMPR6=0x06DC;
//Enable T3 underflow Interrupt
//EvbRegs.EVBIMRA.bit.T3UFINT=1;
//EvbRegs.EVBIFRA.bit.T3UFINT=1;
// Disable T3 Full compare PWM out
EvbRegs.ACTRB.all=0x0000;
// Timer 4,contunuous Up Mode, Reload when counter is 0,Diable timer
// Disable compare operation, 150MHz/64
EvbRegs.T4CON.all=0x160A;//0x170A
//Enable capture 4,5,6 select timer 4,detects falling edge
EvbRegs.CAPCONB.all=0x30A8;
EvbRegs.T4CNT=0;
EvbRegs.T4PR=0xFFFF;
EvbRegs.T4CMPR=0x0494;
//Enable Capture 4,5,6 interrupt and compare interrupt
EvbRegs.EVBIMRB.bit.T4CINT=1;
EvbRegs.EVBIFRB.bit.T4CINT=1;
EvbRegs.EVBIMRC.all=0x0007;
//EvbRegs.EVBIMRC.bit.CAP4INT=1;
//EvbRegs.EVBIMRC.bit.CAP5INT=1;
//EvbRegs.EVBIMRC.bit.CAP6INT=1;
EvbRegs.EVBIFRC.all=0x0007;
//EvbRegs.EVBIFRC.bit.CAP4INT=1;
//EvbRegs.EVBIFRC.bit.CAP5INT=1;
//EvbRegs.EVBIFRC.bit.CAP6INT=1;
EvbRegs.EXTCONB.all=0;
//Enable timer
EvaRegs.T1CON.bit.TENABLE=1;
EvaRegs.T2CON.bit.TENABLE=1;
EvbRegs.T3CON.bit.TENABLE=1;
EvbRegs.T4CON.bit.TENABLE=1;
}
void sInitSCI(void)
{
// One stop bit, no parity, 8-bit character length
SciaRegs.SCICCR.all=0x07;
// Enable transmit and receive
SciaRegs.SCICTL1.all=0x03;
// 2400
SciaRegs.SCIHBAUD=0x07;//0x0F;
SciaRegs.SCILBAUD=0xA0;//0x41;
// Enable Receive interrupt and transmit interrupt
SciaRegs.SCICTL2.all=0x03;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
}
void sInitSPI(void)
{
SpiaRegs.SPICCR.bit.RESET=0;
SpiaRegs.SPICCR.bit.CLKPOLARITY=0; //ywt/070322A
SpiaRegs.SPICCR.bit.SPICHAR=0x07;
SpiaRegs.SPICTL.bit.OVERRUN=0;
SpiaRegs.SPICTL.bit.CLK_PHASE=1; //ywt/070322A
SpiaRegs.SPICTL.bit.MASTER_SLAVE=1;
SpiaRegs.SPICTL.bit.TALK=1;
SpiaRegs.SPICTL.bit.SPIINTENA=0;
//SpiaRegs.SPIBRR=35; //1MHz
SpiaRegs.SPIBRR=127; //1MHz
SpiaRegs.SPICCR.bit.RESET=1;
}
void sInitEXINTF(void)
{
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 1;
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;
XintfRegs.XTIMING6.bit.XWRACTIVE = 4;
XintfRegs.XTIMING6.bit.XWRTRAIL = 2;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 1;
XintfRegs.XTIMING6.bit.XRDACTIVE = 4;
XintfRegs.XTIMING6.bit.XRDTRAIL = 1;
// do not double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;
// Zone will not sample READY
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
}
void sInitCAN(void)
{
asm(" EALLOW");
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/
ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaRegs.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANRIOC.bit.RXFUNC = 1;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaRegs.CANMC.bit.SCB = 1;
ECanaRegs.CANBTC.bit.BRPREG = 9;
ECanaRegs.CANBTC.bit.TSEG2REG = 2;
ECanaRegs.CANBTC.bit.TSEG1REG = 10;
ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
while(ECanaRegs.CANBTC.bit.TSEG2REG ==0 || ECanaRegs.CANBTC.bit.TSEG1REG == 0){}
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MCF register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MCF must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
/* Clear all TAn bits */
ECanaRegs.CANTA.all = 0xFFFFFFFF;
/* Clear all RMPn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF;
/* Clear all interrupt flag bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters */
// ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
//
// while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
//
// ECanaRegs.CANBTC.bit.BRPREG = 9;
// ECanaRegs.CANBTC.bit.TSEG2REG = 2;
// ECanaRegs.CANBTC.bit.TSEG1REG = 10;
//
// ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
// while(ECanaRegs.CANES.bit.CCE == !0 ) {} // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
}
/*********************************************************************
* Function: DelayUs() *
* Description: Implements a time delay. *
* DSP: TMS320F2812 *
* Last Modified: 06/28/02 *
* Include files: none *
* Function Prototype: void DelayUs(volatile Uint16) *
* Useage: DelayUs(Usec); *
* Input Parameters: Uint16 Usec = time delay in microseconds *
* Return Value: none *
* Notes: The execution time of this routine is rough, based upon a *
* 150MHz CPUCLK. It has been tested using all optimization *
* levels of the compiler to give approximately a 1us inner *
* loop. *
*********************************************************************/
void DelayUs( volatile unsigned int Usec )
{
while( Usec-- ) // 1us loop at 150MHz CPUCLK
{
asm(" RPT #139 || NOP");
}
}
long time=0;
void main(void)
{
//Initial DSP
sInitialDSP();
EALLOW;
GpioMuxRegs.GPAMUX.all=0x0000;
GpioMuxRegs.GPADIR.all=0x0028;
GpioMuxRegs.GPAQUAL.all=0x0000;
EDIS;
// asm(" clrc INTM");
// asm(" clrc DBGM");
for(;;)
{
if(time<30000)
{
GpioDataRegs.GPADAT.bit.GPIOA5=1;
GpioDataRegs.GPADAT.bit.GPIOA4=0;
GpioDataRegs.GPADAT.bit.GPIOA3=1;
time++;
}
else if(time<50000)
{
GpioDataRegs.GPADAT.bit.GPIOA5=0;
GpioDataRegs.GPADAT.bit.GPIOA4=1;
GpioDataRegs.GPADAT.bit.GPIOA3=0;
time++;
}
else
{
time=0;
}
}
}
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