📄 main.asm
字号:
; | /M1/L0/L1/H0 internal
; 352 | // control registers bit have to be enabled. The bits are in Device emu
; | lation registers.
;----------------------------------------------------------------------
EALLOW
.dwpsn "main.c",353,4
;----------------------------------------------------------------------
; 353 | DevEmuRegs.M0RAMDFT = 0x0300;
;----------------------------------------------------------------------
MOVW DP,#_DevEmuRegs+208
MOV @_DevEmuRegs+208,#768 ; |353|
.dwpsn "main.c",354,4
;----------------------------------------------------------------------
; 354 | DevEmuRegs.M1RAMDFT = 0x0300;
;----------------------------------------------------------------------
MOV @_DevEmuRegs+209,#768 ; |354|
.dwpsn "main.c",355,4
;----------------------------------------------------------------------
; 355 | DevEmuRegs.L0RAMDFT = 0x0300;
;----------------------------------------------------------------------
MOV @_DevEmuRegs+210,#768 ; |355|
.dwpsn "main.c",356,4
;----------------------------------------------------------------------
; 356 | DevEmuRegs.L1RAMDFT = 0x0300;
;----------------------------------------------------------------------
MOV @_DevEmuRegs+211,#768 ; |356|
.dwpsn "main.c",357,4
;----------------------------------------------------------------------
; 357 | DevEmuRegs.H0RAMDFT = 0x0300;
; 360 | // Disable watchdog module
;----------------------------------------------------------------------
MOV @_DevEmuRegs+212,#768 ; |357|
.dwpsn "main.c",361,4
;----------------------------------------------------------------------
; 361 | SysCtrlRegs.WDCR= 0x0068;
; 363 | // Initalize PLL
;----------------------------------------------------------------------
MOVW DP,#_SysCtrlRegs+25
MOV @_SysCtrlRegs+25,#104 ; |361|
.dwpsn "main.c",364,4
;----------------------------------------------------------------------
; 364 | SysCtrlRegs.PLLCR = 0xA;
; 365 | // Wait for PLL to lock
;----------------------------------------------------------------------
MOV @_SysCtrlRegs+17,#10 ; |364|
.dwpsn "main.c",366,8
;----------------------------------------------------------------------
; 366 | for(i= 0; i< 5000; i++){}
;----------------------------------------------------------------------
MOV *-SP[1],#0 ; |366|
.dwpsn "main.c",366,14
;----------------------------------------------------------------------
; 368 | // HISPCP/LOSPCP prescale register settings.
; 369 | // high speed clock = SYSCLKOUT/1 (EVA,EVB,ADC)
;----------------------------------------------------------------------
CMP *-SP[1],#5000 ; |366|
B L6,HIS ; |366|
; branchcc occurs ; |366|
L5:
DW$L$_sInitSysCtrl$2$B:
.dwpsn "main.c",366,23
INC *-SP[1] ; |366|
.dwpsn "main.c",366,14
CMP *-SP[1],#5000 ; |366|
B L5,LO ; |366|
; branchcc occurs ; |366|
DW$L$_sInitSysCtrl$2$E:
L6:
.dwpsn "main.c",370,4
;----------------------------------------------------------------------
; 370 | SysCtrlRegs.HISPCP.all = 0x0000;
; 371 | // low speed clock = SYSCLKOUT/4 (SCIA,SCIB,SPI,McBSP)
;----------------------------------------------------------------------
MOVW DP,#_SysCtrlRegs+10
MOV @_SysCtrlRegs+10,#0 ; |370|
.dwpsn "main.c",372,4
;----------------------------------------------------------------------
; 372 | SysCtrlRegs.LOSPCP.all = 0x0002;
; 373 | // Peripheral clock enables set for the selected peripherals.
;----------------------------------------------------------------------
MOV @_SysCtrlRegs+11,#2 ; |372|
.dwpsn "main.c",374,4
;----------------------------------------------------------------------
; 374 | SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x0001 ; |374|
.dwpsn "main.c",375,4
;----------------------------------------------------------------------
; 375 | SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x0002 ; |375|
.dwpsn "main.c",376,4
;----------------------------------------------------------------------
; 376 | SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x0400 ; |376|
.dwpsn "main.c",377,4
;----------------------------------------------------------------------
; 377 | SysCtrlRegs.PCLKCR.bit.SCIENCLKB=0;
;----------------------------------------------------------------------
AND @_SysCtrlRegs+12,#0xf7ff ; |377|
.dwpsn "main.c",378,4
;----------------------------------------------------------------------
; 378 | SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;
;----------------------------------------------------------------------
AND @_SysCtrlRegs+12,#0xefff ; |378|
.dwpsn "main.c",379,4
;----------------------------------------------------------------------
; 379 | SysCtrlRegs.PCLKCR.bit.SPIENCLK=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x0100 ; |379|
.dwpsn "main.c",380,4
;----------------------------------------------------------------------
; 380 | SysCtrlRegs.PCLKCR.bit.ECANENCLK=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x4000 ; |380|
.dwpsn "main.c",381,4
;----------------------------------------------------------------------
; 381 | SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;
;----------------------------------------------------------------------
OR @_SysCtrlRegs+12,#0x0008 ; |381|
.dwpsn "main.c",382,4
;----------------------------------------------------------------------
; 382 | EDIS;
;----------------------------------------------------------------------
EDIS
.dwpsn "main.c",384,1
SUBB SP,#2
.dwcfa 0x1d, -2
SPM #0
LRETR
; return occurs
DW$37 .dwtag DW_TAG_loop
.dwattr DW$37, DW_AT_name("C:/CCStudio_v3.1/MyProjects/2812Test/APP/asm/main.asm:L5:1:1225184731")
.dwattr DW$37, DW_AT_begin_file("main.c")
.dwattr DW$37, DW_AT_begin_line(0x16e)
.dwattr DW$37, DW_AT_end_line(0x16e)
DW$38 .dwtag DW_TAG_loop_range
.dwattr DW$38, DW_AT_low_pc(DW$L$_sInitSysCtrl$2$B)
.dwattr DW$38, DW_AT_high_pc(DW$L$_sInitSysCtrl$2$E)
.dwendtag DW$37
.dwattr DW$35, DW_AT_end_file("main.c")
.dwattr DW$35, DW_AT_end_line(0x180)
.dwattr DW$35, DW_AT_end_column(0x01)
.dwendentry
.dwendtag DW$35
.sect "ramfuncs"
.global _sInitFlash
DW$39 .dwtag DW_TAG_subprogram, DW_AT_name("sInitFlash"), DW_AT_symbol_name("_sInitFlash")
.dwattr DW$39, DW_AT_low_pc(_sInitFlash)
.dwattr DW$39, DW_AT_high_pc(0x00)
.dwattr DW$39, DW_AT_begin_file("main.c")
.dwattr DW$39, DW_AT_begin_line(0x188)
.dwattr DW$39, DW_AT_begin_column(0x06)
.dwpsn "main.c",393,1
.dwfde DW$CIE
;----------------------------------------------------------------------
; 392 | void sInitFlash(void)
;----------------------------------------------------------------------
;***************************************************************
;* FNAME: _sInitFlash FR SIZE: 0 *
;* *
;* FUNCTION ENVIRONMENT *
;* *
;* FUNCTION PROPERTIES *
;* 0 Parameter, 0 Auto, 0 SOE *
;***************************************************************
_sInitFlash:
.dwcfa 0x1d, -2
.dwcfa 0x1c, 26, 0
.dwcfa 0x09, 40, 26
.dwpsn "main.c",394,4
;----------------------------------------------------------------------
; 394 | EALLOW;
; 395 | //Enable Flash Pipeline mode to improve performance
; 396 | //of code executed from Flash.
;----------------------------------------------------------------------
EALLOW
.dwpsn "main.c",397,4
;----------------------------------------------------------------------
; 397 | FlashRegs.FOPT.bit.ENPIPE = 1;
; 399 | // CAUTION
; 400 | //Minimum waitstates required for the flash operating
; 401 | //at a given CPU rate must be characterized by TI.
; 402 | //Refer to the datasheet for the latest information.
; 404 | //Set the Random Waitstate for the Flash
;----------------------------------------------------------------------
MOVW DP,#_FlashRegs
OR @_FlashRegs,#0x0001 ; |397|
.dwpsn "main.c",405,4
;----------------------------------------------------------------------
; 405 | FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;//lg/030905 5;
; 407 | //Set the Paged Waitstate for the Flash
;----------------------------------------------------------------------
AND AL,@_FlashRegs+6,#0xfff0 ; |405|
ORB AL,#0x05 ; |405|
MOV @_FlashRegs+6,AL ; |405|
.dwpsn "main.c",408,4
;----------------------------------------------------------------------
; 408 | FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;//lg/030905 5;
; 410 | // CAUTION
; 411 | //Minimum cycles required to move between power states
; 412 | //at a given CPU rate must be characterized by TI.
; 413 | //Refer to the datasheet for the latest information.
; 415 | //For now use the default count
; 417 | //Set number of cycles to transition from sleep to standby
;----------------------------------------------------------------------
AND AL,@_FlashRegs+6,#0xf0ff ; |408|
OR AL,#0x0500 ; |408|
MOV @_FlashRegs+6,AL ; |408|
.dwpsn "main.c",418,4
;----------------------------------------------------------------------
; 418 | FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
; 420 | //Set number of cycles to transition from standby to active
;----------------------------------------------------------------------
OR @_FlashRegs+4,#0x00ff ; |418|
.dwpsn "main.c",421,4
;----------------------------------------------------------------------
; 421 | FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
;----------------------------------------------------------------------
OR @_FlashRegs+5,#0x00ff ; |421|
.dwpsn "main.c",422,4
;----------------------------------------------------------------------
; 422 | EDIS;
;----------------------------------------------------------------------
EDIS
.dwpsn "main.c",423,1
SPM #0
LRETR
; return occurs
.dwattr DW$39, DW_AT_end_file("main.c")
.dwattr DW$39, DW_AT_end_line(0x1a7)
.dwattr DW$39, DW_AT_end_column(0x01)
.dwendentry
.dwendtag DW$39
.sect ".text"
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