📄 main.asm
字号:
B L4,HIS ; |262|
; branchcc occurs ; |262|
L3:
DW$L$_sInitialDSP$2$B:
.dwpsn "main.c",264,6
;----------------------------------------------------------------------
; 264 | *pDestAddr++ = *pSourceAddr++;
;----------------------------------------------------------------------
MOVL XAR4,*-SP[2] ; |264|
MOVL XAR6,*XAR4++ ; |264|
MOVL *-SP[2],XAR4 ; |264|
MOVL XAR4,*-SP[4] ; |264|
MOVL ACC,XAR4 ; |264|
ADDB ACC,#2 ; |264|
MOVL *-SP[4],ACC ; |264|
MOVL *+XAR4[0],XAR6 ; |264|
.dwpsn "main.c",262,34
INC *-SP[5] ; |262|
.dwpsn "main.c",262,13
CMP *-SP[5],#4096 ; |262|
B L3,LO ; |262|
; branchcc occurs ; |262|
DW$L$_sInitialDSP$2$E:
L4:
.dwpsn "main.c",267,2
;----------------------------------------------------------------------
; 267 | sInitFlash();
; 269 | #endif
; 271 | // Step 2. Initialize Event Manager registers for the specific applicat
; | ion
;----------------------------------------------------------------------
LCR #_sInitFlash ; |267|
; call occurs [#_sInitFlash] ; |267|
.dwpsn "main.c",274,2
;----------------------------------------------------------------------
; 274 | sInitEV();
; 276 | // Step 3. Initialize AD registers
;----------------------------------------------------------------------
LCR #_sInitEV ; |274|
; call occurs [#_sInitEV] ; |274|
.dwpsn "main.c",278,2
;----------------------------------------------------------------------
; 278 | sInitAdc();
; 280 | // Step 4. Select GPIO for the device or for the specific application:
;----------------------------------------------------------------------
LCR #_sInitAdc ; |278|
; call occurs [#_sInitAdc] ; |278|
.dwpsn "main.c",282,2
;----------------------------------------------------------------------
; 282 | sInitGpio();
; 284 | // Step 5. Initialize SCI registers
;----------------------------------------------------------------------
LCR #_sInitGpio ; |282|
; call occurs [#_sInitGpio] ; |282|
.dwpsn "main.c",286,2
;----------------------------------------------------------------------
; 286 | sInitSCI();
; 288 | // Step 6. Initialize CAN registers
; 290 | //sInitCAN();
; 292 | // Step 7. Initialize SPI registers
;----------------------------------------------------------------------
LCR #_sInitSCI ; |286|
; call occurs [#_sInitSCI] ; |286|
.dwpsn "main.c",294,2
;----------------------------------------------------------------------
; 294 | sInitSPI();
; 296 | // Step 8. Initialize PIE vector table:
; 297 | // The PIE vector table is initialized with pointers to shell Interrupt
; |
; 298 | // Service Routines (ISR). The shell routines are found in DSP28_Defau
; | ltIsr.c.
; 299 | // Insert user specific ISR code in the appropriate shell ISR routine i
; | n
; 300 | // the DSP28_DefaultIsr.c file.
; 303 | // enable EXT Interrupt 2 and Detect on rising edge
;----------------------------------------------------------------------
LCR #_sInitSPI ; |294|
; call occurs [#_sInitSPI] ; |294|
.dwpsn "main.c",304,2
;----------------------------------------------------------------------
; 304 | XIntruptRegs.XINT2CR.all = 5;
; 306 | // Step 9. Initialize extern IO
; 307 | // sInitEXTIO();
; 308 | // Disable and clear all CPU interrupts:
;----------------------------------------------------------------------
MOVW DP,#_XIntruptRegs+1
MOV @_XIntruptRegs+1,#5 ; |304|
.dwpsn "main.c",309,2
;----------------------------------------------------------------------
; 309 | DINT;
;----------------------------------------------------------------------
setc INTM
.dwpsn "main.c",310,2
;----------------------------------------------------------------------
; 310 | IER = 0x0000;
;----------------------------------------------------------------------
AND IER,#0 ; |310|
.dwpsn "main.c",311,2
;----------------------------------------------------------------------
; 311 | IFR = 0x0000;
; 313 | //Enbale PIE group 1 interrupt 5 for XINT2
;----------------------------------------------------------------------
AND IFR,#0 ; |311|
.dwpsn "main.c",315,6
;----------------------------------------------------------------------
; 315 | PieCtrlRegs.PIEIER1.bit.INTx5 =1;
; 317 | // Enable PIE group 2 interrupt 4 for T1PINT,interrupt 6 for T1UFINT
;----------------------------------------------------------------------
MOVW DP,#_PieCtrlRegs+2
OR @_PieCtrlRegs+2,#0x0010 ; |315|
.dwpsn "main.c",318,5
;----------------------------------------------------------------------
; 318 | PieCtrlRegs.PIEIER2.bit.INTx4=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+4,#0x0008 ; |318|
.dwpsn "main.c",319,5
;----------------------------------------------------------------------
; 319 | PieCtrlRegs.PIEIER2.bit.INTx6=1;
; 321 | // Enalbe PIE group 3 interrupt 2 for T2CINT
; 322 | // PieCtrlRegs.PIEIER3.bit.INTx2=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+4,#0x0020 ; |319|
.dwpsn "main.c",323,5
;----------------------------------------------------------------------
; 323 | PieCtrlRegs.PIEIER3.bit.INTx5=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+6,#0x0010 ; |323|
.dwpsn "main.c",324,5
;----------------------------------------------------------------------
; 324 | PieCtrlRegs.PIEIER3.bit.INTx6=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+6,#0x0020 ; |324|
.dwpsn "main.c",325,5
;----------------------------------------------------------------------
; 325 | PieCtrlRegs.PIEIER3.bit.INTx7=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+6,#0x0040 ; |325|
.dwpsn "main.c",327,5
;----------------------------------------------------------------------
; 327 | PieCtrlRegs.PIEIER5.bit.INTx2=1;
; 328 | // Enable PIE group 5 interrupt 4,5,6 for CAPINT4,5,6
;----------------------------------------------------------------------
OR @_PieCtrlRegs+10,#0x0002 ; |327|
.dwpsn "main.c",329,5
;----------------------------------------------------------------------
; 329 | PieCtrlRegs.PIEIER5.bit.INTx5=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+10,#0x0010 ; |329|
.dwpsn "main.c",330,5
;----------------------------------------------------------------------
; 330 | PieCtrlRegs.PIEIER5.bit.INTx6=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+10,#0x0020 ; |330|
.dwpsn "main.c",331,5
;----------------------------------------------------------------------
; 331 | PieCtrlRegs.PIEIER5.bit.INTx7=1;
; 334 | // Enable PIE group 9 interrupt 1 for SCIRXINTA, 5 for ECAN0INT,6 for E
; | CAN1INT
;----------------------------------------------------------------------
OR @_PieCtrlRegs+10,#0x0040 ; |331|
.dwpsn "main.c",335,5
;----------------------------------------------------------------------
; 335 | PieCtrlRegs.PIEIER9.bit.INTx1=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+18,#0x0001 ; |335|
.dwpsn "main.c",336,5
;----------------------------------------------------------------------
; 336 | PieCtrlRegs.PIEIER9.bit.INTx2=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+18,#0x0002 ; |336|
.dwpsn "main.c",337,5
;----------------------------------------------------------------------
; 337 | PieCtrlRegs.PIEIER9.bit.INTx5=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+18,#0x0010 ; |337|
.dwpsn "main.c",338,5
;----------------------------------------------------------------------
; 338 | PieCtrlRegs.PIEIER9.bit.INTx6=1;
;----------------------------------------------------------------------
OR @_PieCtrlRegs+18,#0x0020 ; |338|
.dwpsn "main.c",340,1
SUBB SP,#6
.dwcfa 0x1d, -2
SPM #0
LRETR
; return occurs
DW$33 .dwtag DW_TAG_loop
.dwattr DW$33, DW_AT_name("C:/CCStudio_v3.1/MyProjects/2812Test/APP/asm/main.asm:L3:1:1225184731")
.dwattr DW$33, DW_AT_begin_file("main.c")
.dwattr DW$33, DW_AT_begin_line(0x106)
.dwattr DW$33, DW_AT_end_line(0x109)
DW$34 .dwtag DW_TAG_loop_range
.dwattr DW$34, DW_AT_low_pc(DW$L$_sInitialDSP$2$B)
.dwattr DW$34, DW_AT_high_pc(DW$L$_sInitialDSP$2$E)
.dwendtag DW$33
.dwattr DW$29, DW_AT_end_file("main.c")
.dwattr DW$29, DW_AT_end_line(0x154)
.dwattr DW$29, DW_AT_end_column(0x01)
.dwendentry
.dwendtag DW$29
.sect ".text"
.global _sInitSysCtrl
DW$35 .dwtag DW_TAG_subprogram, DW_AT_name("sInitSysCtrl"), DW_AT_symbol_name("_sInitSysCtrl")
.dwattr DW$35, DW_AT_low_pc(_sInitSysCtrl)
.dwattr DW$35, DW_AT_high_pc(0x00)
.dwattr DW$35, DW_AT_begin_file("main.c")
.dwattr DW$35, DW_AT_begin_line(0x15a)
.dwattr DW$35, DW_AT_begin_column(0x06)
.dwpsn "main.c",347,1
.dwfde DW$CIE
;----------------------------------------------------------------------
; 346 | void sInitSysCtrl(void)
;----------------------------------------------------------------------
;***************************************************************
;* FNAME: _sInitSysCtrl FR SIZE: 2 *
;* *
;* FUNCTION ENVIRONMENT *
;* *
;* FUNCTION PROPERTIES *
;* 0 Parameter, 1 Auto, 0 SOE *
;***************************************************************
_sInitSysCtrl:
;----------------------------------------------------------------------
; 348 | unsigned int i;
;----------------------------------------------------------------------
.dwcfa 0x1d, -2
.dwcfa 0x1c, 26, 0
.dwcfa 0x09, 40, 26
ADDB SP,#2
.dwcfa 0x1d, -4
DW$36 .dwtag DW_TAG_variable, DW_AT_name("i"), DW_AT_symbol_name("_i")
.dwattr DW$36, DW_AT_type(*DW$T$11)
.dwattr DW$36, DW_AT_location[DW_OP_breg20 -1]
.dwpsn "main.c",349,4
;----------------------------------------------------------------------
; 349 | EALLOW;
; 351 | // On TMX samples, to get the best performance of on chip RAM blocks M0
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