📄 initial.c
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//Set the Paged Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5;//lg/030905 5;
// CAUTION
//Minimum cycles required to move between power states
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//For now use the default count
//Set number of cycles to transition from sleep to standby
FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF;
//Set number of cycles to transition from standby to active
FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF;
EDIS;
}
//---------------------------------------------------------------------------
// KickDog:
//---------------------------------------------------------------------------
// This function resets the watchdog timer.
// Enable this function for using KickDog in the application
/*
void sKickDog(void)
{
EALLOW;
SysCtrlRegs.WDKEY = 0x0055;
SysCtrlRegs.WDKEY = 0x00AA;
EDIS;
}
*/
//---------------------------------------------------------------------------
// InitAdc:
//---------------------------------------------------------------------------
// This function initializes ADC to a known state.
//
void sInitAdc(void)
{
extern void DSP28x_usDelay(unsigned long Count);
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap and reference circuitry.
// After a 5ms delay the rest of the ADC can be powered up. After ADC
// powerup, another 20us delay is required before performing the first
// ADC conversion. Please note that for the delay function below to
// operate correctly the CPU_CLOCK_SPEED define statement in the
// DSP28_Device.h file must contain the correct CPU clock period in
// nanoseconds. For example:
//
// #define CPU_CLOCK_SPEED 6.6667L // for a 150MHz CPU clock speed
//This was done in the InitSysCtrl() function in DSP28_SysCtrl.c
//asm(" EALLOW");
//SysCtrlRegs.PCLKCR.bit.ADCENCLK = 1; // Power up clocks to ADC
//SysCtrlRegs.WDCR = 0x6F; // Disable WD
//asm(" EDIS");
/*** Reset the ADC module ***/
AdcRegs.ADCTRL1.bit.RESET = 1; // Reset the ADC module
asm(" RPT #20 || NOP"); // Must wait 12-cycles (worst-case) for ADC reset to take effect // for test ywt/061214A
AdcRegs.ADCTRL3.all = 0x00C6; // first power-up ref and bandgap circuits
//AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;// Power up bandgap/reference circuitry
DelayUs(10000); //According to spru060b(200407).pdf which the latest user guild , wait 7ms before setting ADCPWDN//lg/040803 // for test ywt/061214A
AdcRegs.ADCTRL3.bit.ADCPWDN = 1; // Set ADCPWDN=1 to power main ADC
DelayUs(200); // Wait 20us before using the ADC
/*
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;// Power up bandgap/reference circuitry
DELAY_US(ADC_usDELAY); // Delay before powering up rest of ADC
AdcRegs.ADCTRL3.bit.ADCPWDN = 1; // Power up rest of ADC
DELAY_US(ADC_usDELAY2); // Delay after powering up ADC
*/
AdcRegs.ADCMAXCONV.all=0x000F;
AdcRegs.ADCCHSELSEQ1.all=0x3210;
AdcRegs.ADCCHSELSEQ2.all=0x7654;
AdcRegs.ADCCHSELSEQ3.all=0xBA98;
AdcRegs.ADCCHSELSEQ4.all=0xFEDC;
//Initial ADC: reset ADC, Set Acquisition window size = 0,so the width of SOC
//pulse is 1, Fclk is selected as CLK/1, Start-stop mode,Cascaded mode
//AdcRegs.ADCTRL1.bit.RESET=1;
//AdcRegs.ADCTRL1.all = 0x2710;
AdcRegs.ADCTRL1.all=0x2010; //0x4010;
// diable EVB trigger ADC, Reset Seq1,Reset Seq2, Disable ADC Interrupt
//AdcRegs.ADCTRL2.all=0x4040;
//AdcRegs.ADCTRL2.all = 0x0900;
//AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
//AdcRegs.ADCTRL2.all=0x4000;
}
//---------------------------------------------------------------------------
// InitGpio:
//---------------------------------------------------------------------------
// This function initializes the Gpio to a known state.
//
void sInitGpio(void)
{
// Set GPIO A port pins,AL(Bits 7:0)(input)-AH(Bits 15:8) (output) 8bits
// Input Qualifier =0, none
EALLOW;
GpioMuxRegs.GPAMUX.all=0x07FF;
GpioMuxRegs.GPADIR.all=0xE000;
GpioMuxRegs.GPAQUAL.all=0x00FF; // sync clock/510
GpioMuxRegs.GPBMUX.all=0x077F; // ywt/061208C
GpioMuxRegs.GPBDIR.all=0xE080;
GpioMuxRegs.GPBQUAL.all=0x00FF; // Input qualifier disabled
GpioMuxRegs.GPDMUX.all=0x0000; //0x0021; lg/040203
GpioMuxRegs.GPDDIR.all=0x0063; //0x0042; lg/040203
GpioMuxRegs.GPDQUAL.all=0x0000;
GpioMuxRegs.GPEMUX.all=0x0001;
GpioMuxRegs.GPEDIR.all=0x0000;
GpioMuxRegs.GPEQUAL.all=0x0000;
// GpioMuxRegs.GPFMUX.all=0x00FF;
// GpioMuxRegs.GPFDIR.all=0xFF00;
GpioMuxRegs.GPFMUX.all=0x00F7; //ywt/070322A for software control SPI CS line
GpioMuxRegs.GPFDIR.all=0xFF08; //ywt/070322A for software control SPI CS line
// GpioMuxRegs.GPFQUAL.all=0x0000;
GpioMuxRegs.GPGMUX.all=0x0030;
GpioMuxRegs.GPGDIR.all=0x0000;
// GpioMuxRegs.GPGQUAL.all=0x0000;
EDIS;
}
//---------------------------------------------------------------------------
// InitPieCtrl:
//---------------------------------------------------------------------------
// This function initializes the PIE control registers to a known state.
//
void sInitPieCtrl(void)
{
// Disable PIE:
PieCtrlRegs.PIECRTL.bit.ENPIE = 0;
// Clear all PIEIER registers:
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
// Clear all PIEIFR registers:
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
// Enable PIE:
PieCtrlRegs.PIECRTL.bit.ENPIE = 1;
PieCtrlRegs.PIEACK.all = 0xFFFF;
}
//---------------------------------------------------------------------------
// InitPieVectTable:
//---------------------------------------------------------------------------
// This function initializes the PIE vector table to a known state.
// This function must be executed after boot time.
//
void sInitPieVectTable(void)
{
int i;
unsigned long *Source = (void *) &PieVectTableInit;
unsigned long *Dest = (void *) &PieVectTable;
EALLOW;
for(i=0; i < 128; i++)
*Dest++ = *Source++;
EDIS;
// Enable the PIE Vector Table
PieCtrlRegs.PIECRTL.bit.ENPIE = 1;
}
//---------------------------------------------------------------------------
//InitEV:
//---------------------------------------------------------------------------
//This function initializes the Evernt manager register
void sInitEV(void)
{
//disable PDPINTA & PDPINTB
EvaRegs.EVAIMRA.bit.PDPINTA=0;
EvaRegs.EVAIFRA.bit.PDPINTA=1;
EvbRegs.EVBIMRA.bit.PDPINTB=0;
EvbRegs.EVBIFRA.bit.PDPINTB=1;
//Disable compare Trip,diable compare output,compare out put force low
//Enable T1,T2 PWM output for six independence PWM
EvaRegs.GPTCONA.all=0x0040;
// Initialize EVA Timer 1:
// Setup Timer 1 Registers (EV A)
// Continuous Up/Down Mode, Reload when counter is 0,Disable timer
// Disalbe timer compare operation,150MHz
//EvaRegs.T1CON.all=0x0800;
// Enable compare output for six independence PWM
EvaRegs.T1CON.all=0x0802;
//Enable full compare, load when T1CNT=0 or T1CNT=T1PR,
//Active control register reload when T1CNT=0 or T1CNT=T1PR.
//EvaRegs.COMCONA.all=0xA600;
EvaRegs.COMCONA.all=0xAA00;
// 1.5us dead time, 150MHz/16, Dead-band timer period=14
//EvaRegs.DBTCONA.all=0x0EF0;
EvaRegs.DBTCONA.all=0x0CF0; //1.28us dead time
// disable PWM 1-6
EvaRegs.ACTRA.all=0;// three pairs PWM must be set together
// EvaRegs.ACTRA.bit.CMP2ACT=2;
// EvaRegs.ACTRA.bit.CMP1ACT=1;
//
// EvaRegs.ACTRA.bit.CMP4ACT=2;
// EvaRegs.ACTRA.bit.CMP3ACT=1;
//
//
// EvaRegs.ACTRA.bit.CMP6ACT=1;
// EvaRegs.ACTRA.bit.CMP5ACT=2;
EvaRegs.T1CNT=0;
EvaRegs.T1PR=0x0F42;
EvaRegs.T1CMPR=0;
//enable compare for six independent PWM
//EvaRegs.T1CMPR=0x0200;
// PWM 1-6 test
//EvaRegs.CMPR1=0x05DC;
//EvaRegs.CMPR2=0x05DC;
//EvaRegs.CMPR3=0x05DC;
//Enable T1 Period interrupt and T1 Underflow interrupt
EvaRegs.EVAIMRA.bit.T1PINT=1;
EvaRegs.EVAIFRA.bit.T1PINT=1;
EvaRegs.EVAIMRA.bit.T1UFINT=1;
EvaRegs.EVAIFRA.bit.T1UFINT=1;
//Use timer2's compare interrupt to generate 1ms TimerTick
//contunuous Up Mode, Reload when counter is 0,Diable timer
// Enable compare operation, 150MHz/64
//EvaRegs.T2CON.all=0x160A;
//Disable compare Trip,diable compare output,compare out put force low
//Enable T1,T2 PWM output for six independence PWM
EvaRegs.T2CON.all=0x0802;
//Enable capture 1,2,3 select timer 4,detects falling edge
//EvaRegs.CAPCON.all=0x30A8;
EvaRegs.CAPCON.all=0x30A8;//LC/040510
EvaRegs.T2CNT=0;
EvaRegs.T2PR=0x0F42;
//EvaRegs.T2CMPR=0x0493;
//Enable Capture 4,5,6 interrupt //and compare interrupt
//EvaRegs.EVAIMRB.bit.T2CINT=1;
//EvaRegs.EVAIFRB.bit.T2CINT=1;
EvaRegs.CAPFIFO.all=0x1000;//lc/040531
EvaRegs.EVAIMRC.all=0x0007;
//EvaRegs.EVAIMRC.bit.CAP1INT=1;
//EvaRegs.EVAIMRC.bit.CAP2INT=1;
//EvaRegs.EVAIMRC.bit.CAP3INT=1;
EvaRegs.EVAIFRC.all=0x0007;
//EvaRegs.EVAIFRC.bit.CAP1INT=1;
//EvaRegs.EVAIFRC.bit.CAP2INT=1;
//EvaRegs.EVAIFRC.bit.CAP3INT=1;
EvaRegs.EXTCON.all=0x0000;
//Disable compare Trip,diable compare output,compare out put force low
//EvbRegs.GPTCONB.all=0x0000;
// Enable Output Compare PWM ,t4 force low t3 active high
EvbRegs.GPTCONB.all=0x0044; // for test ywt/061208A
// timer3 continuous Up/Down Mode, Reload when counter is 0
// Disable timer, Disable timer compare operation,150MHz
//EvbRegs.T3CON.all=0x0800;
// Enable T3 CMP/PWM, for six independence PWM
EvbRegs.T3CON.all=0x0802;
//Enable full compare, load when T1CNT=0 or T1CNT=T1PR,
//Active control register reload when T1CNT=0 or T1CNT=T1PR.
EvbRegs.COMCONB.all=0xA600;
// 1.5us dead time, 150MHz/16, Dead-band timer period=14
EvbRegs.DBTCONB.all=0x0EF0;
EvbRegs.T3CNT=0;
EvbRegs.T3PR=0x0F42;
//EvbRegs.T3CMPR=0x0500;;
//EvbRegs.CMPR4=0x04DC;
//EvbRegs.CMPR5=0x05DC;
//EvbRegs.CMPR6=0x06DC;
//Enable T3 underflow Interrupt
//EvbRegs.EVBIMRA.bit.T3UFINT=1;
//EvbRegs.EVBIFRA.bit.T3UFINT=1;
// Disable T3 Full compare PWM out
EvbRegs.ACTRB.all=0x0000;
// Timer 4,contunuous Up Mode, Reload when counter is 0,Diable timer
// Disable compare operation, 150MHz/64
EvbRegs.T4CON.all=0x160A;//0x170A
//Enable capture 4,5,6 select timer 4,detects falling edge
EvbRegs.CAPCONB.all=0x30A8;
EvbRegs.T4CNT=0;
EvbRegs.T4PR=0xFFFF;
EvbRegs.T4CMPR=0x0494;
//Enable Capture 4,5,6 interrupt and compare interrupt
EvbRegs.EVBIMRB.bit.T4CINT=1;
EvbRegs.EVBIFRB.bit.T4CINT=1;
EvbRegs.EVBIMRC.all=0x0007;
//EvbRegs.EVBIMRC.bit.CAP4INT=1;
//EvbRegs.EVBIMRC.bit.CAP5INT=1;
//EvbRegs.EVBIMRC.bit.CAP6INT=1;
EvbRegs.EVBIFRC.all=0x0007;
//EvbRegs.EVBIFRC.bit.CAP4INT=1;
//EvbRegs.EVBIFRC.bit.CAP5INT=1;
//EvbRegs.EVBIFRC.bit.CAP6INT=1;
EvbRegs.EXTCONB.all=0;
//Enable timer
EvaRegs.T1CON.bit.TENABLE=1;
EvaRegs.T2CON.bit.TENABLE=1;
EvbRegs.T3CON.bit.TENABLE=1;
EvbRegs.T4CON.bit.TENABLE=1;
}
void sInitSCI(void)
{
// One stop bit, no parity, 8-bit character length
SciaRegs.SCICCR.all=0x07;
// Enable transmit and receive
SciaRegs.SCICTL1.all=0x03;
// 2400
SciaRegs.SCIHBAUD=0x07;//0x0F;
SciaRegs.SCILBAUD=0xA0;//0x41;
// Enable Receive interrupt and transmit interrupt
SciaRegs.SCICTL2.all=0x03;
SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset
}
void sInitSPI(void)
{
SpiaRegs.SPICCR.bit.RESET=0;
SpiaRegs.SPICCR.bit.CLKPOLARITY=0; //ywt/070322A
SpiaRegs.SPICCR.bit.SPICHAR=0x07;
SpiaRegs.SPICTL.bit.OVERRUN=0;
SpiaRegs.SPICTL.bit.CLK_PHASE=1; //ywt/070322A
SpiaRegs.SPICTL.bit.MASTER_SLAVE=1;
SpiaRegs.SPICTL.bit.TALK=1;
SpiaRegs.SPICTL.bit.SPIINTENA=0;
//SpiaRegs.SPIBRR=35; //1MHz
SpiaRegs.SPIBRR=127; //1MHz
SpiaRegs.SPICCR.bit.RESET=1;
}
void sInitEXINTF(void)
{
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = SYSCLKOUT
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// Buffer up to 3 writes
XintfRegs.XINTCNF2.bit.WRBUFF = 3;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 1;
// XCLKOUT = XTIMCLK
XintfRegs.XINTCNF2.bit.CLKMODE = 0;
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;
XintfRegs.XTIMING6.bit.XWRACTIVE = 4;
XintfRegs.XTIMING6.bit.XWRTRAIL = 2;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 1;
XintfRegs.XTIMING6.bit.XRDACTIVE = 4;
XintfRegs.XTIMING6.bit.XRDTRAIL = 1;
// do not double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;
// Zone will not sample READY
XintfRegs.XTIMING6.bit.USEREADY = 0;
XintfRegs.XTIMING6.bit.READYMODE = 0;
// Size must be 1,1 - other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
}
void sInitCAN(void)
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