📄 initial.c
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//###########################################################################
//
// FILE: DSP28_Initial.h
//
// TITLE: TMS320F2810 registers define
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// .00 | 17 07 2003 | lg |
//
//###########################################################################
#include "kernel\kernel.h"
#include "module\module.h"
#include "cpu\registers.h"
#include "cpu\IO.h"
#include "app\Interrupt.h"
#include "app\constant.h"
#include "app\app.h"
#include "app\Eeprom.h"
#include "driver\driver.h"
#define ADC_usDELAY 5000L
#define ADC_usDELAY2 20L
#define RunInFlash
const struct PIE_VECT_TABLE PieVectTableInit = {
PIE_RESERVED, // Reserved space
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
PIE_RESERVED,
// Non-Peripheral Interrupts
INT13_ISR, // XINT13 or CPU-Timer 1
INT14_ISR, // CPU-Timer2
DATALOG_ISR, // Datalogging interrupt
RTOSINT_ISR, // RTOS interrupt
EMUINT_ISR, // Emulation interrupt
NMI_ISR, // Non-maskable interrupt
ILLEGAL_ISR, // Illegal operation TRAP
USER0_ISR, // User Defined trap 0
USER1_ISR, // User Defined trap 1
USER2_ISR, // User Defined trap 2
USER3_ISR, // User Defined trap 3
USER4_ISR, // User Defined trap 4
USER5_ISR, // User Defined trap 5
USER6_ISR, // User Defined trap 6
USER7_ISR, // User Defined trap 7
USER8_ISR, // User Defined trap 8
USER9_ISR, // User Defined trap 9
USER10_ISR, // User Defined trap 10
USER11_ISR, // User Defined trap 11
//lg/030905 OSCtxSw, // lg/030801 use trap #31 for OS task switch
// Group 1 PIE Vectors
PDPINTA_ISR, // EV-A
PDPINTB_ISR, // EV-B
rsvd_ISR,
XINT1_ISR,
XINT2_ISR,
ADCINT_ISR, // ADC
TINT0_ISR, // Timer 0
WAKEINT_ISR, // WD
// Group 2 PIE Vectors
CMP1INT_ISR, // EV-A
CMP2INT_ISR, // EV-A
CMP3INT_ISR, // EV-A
T1PINT_ISR, // EV-A
T1CINT_ISR, // EV-A
T1UFINT_ISR, // EV-A
T1OFINT_ISR, // EV-A
rsvd_ISR,
// Group 3 PIE Vectors
T2PINT_ISR, // EV-A
T2CINT_ISR, // EV-A
T2UFINT_ISR, // EV-A
T2OFINT_ISR, // EV-A
CAPINT1_ISR, // EV-A
CAPINT2_ISR, // EV-A
CAPINT3_ISR, // EV-A
rsvd_ISR,
// Group 4 PIE Vectors
CMP4INT_ISR, // EV-B
CMP5INT_ISR, // EV-B
CMP6INT_ISR, // EV-B
T3PINT_ISR, // EV-B
T3CINT_ISR, // EV-B
T3UFINT_ISR, // EV-B
T3OFINT_ISR, // EV-B
rsvd_ISR,
// Group 5 PIE Vectors
T4PINT_ISR, // EV-B
T4CINT_ISR, // EV-B
T4UFINT_ISR, // EV-B
T4OFINT_ISR, // EV-B
CAPINT4_ISR, // EV-B
CAPINT5_ISR, // EV-B
CAPINT6_ISR, // EV-B
rsvd_ISR,
// Group 6 PIE Vectors
SPIRXINTA_ISR, // SPI-A
SPITXINTA_ISR, // SPI-A
rsvd_ISR,
rsvd_ISR,
MRINTA_ISR, // McBSP-A
MXINTA_ISR, // McBSP-A
rsvd_ISR,
rsvd_ISR,
// Group 7 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 8 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 9 PIE Vectors
SCIRXINTA_ISR, // SCI-A
SCITXINTA_ISR, // SCI-A
SCIRXINTB_ISR, // SCI-B
SCITXINTB_ISR, // SCI-B
ECAN0INTA_ISR, // eCAN
ECAN1INTA_ISR, // eCAN
rsvd_ISR,
rsvd_ISR,
// Group 10 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 11 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
// Group 12 PIE Vectors
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
rsvd_ISR,
};
INT16U wInputModule;
INT16U wOutputModule;
// Functions that will be run from RAM need to be assigned to
// a different section. This section will then be mapped using
// the linker cmd file.
#pragma CODE_SECTION(sInitFlash, "ramfuncs");
// Information on the location of functions that are going
// to be relocated to RAM
#define RAM_FUNC_LOAD 0x3EC000 // Source location in Flash
#define RAM_FUNC_LENGTH 0x001000 // Number of 32-bit values to copy 2000(1000*2)
#define RAM_FUNC_RUN 0x008000
void sInitSysCtrl(void);
void sInitFlash(void);
void sInitAdc(void);
void sInitGpio(void);
void sInitPieCtrl(void);
void sInitPieVectTable(void);
void sInitEV(void);
void sInitSCI(void);
void sInitSPI(void);
void sInitEXINTF(void);
//void sInitCAN(void);
void sADCalibration(void);
void DelayUs(volatile unsigned int); //function prototype
void sInitEXTIO(void);
INT16S swGetwADCOffsetA();
INT16S swGetwADCCoefA();
INT16S swGetwREF125A();
INT16S swGetwREF250A();
INT16S wREF125A;
INT16S wREF250A;
void sInitialDSP(void)
{
unsigned long * pSourceAddr;
unsigned long * pDestAddr;
unsigned int i;
// Step 1. Initialize System Control registers, PLL, WatchDog, Clocks to default state:
sInitSysCtrl();
// Disable and clear all CPU interrupts:
DINT;
IER = 0x0000;
IFR = 0x0000;
// Initialize Pie Control Registers To Default State:
// This function is found in the DSP28_PieCtrl.c file.
sInitPieCtrl();
// Initialize the PIE Vector Table To a Known State:
// This function is found in DSP28_PieVect.c.
// This function populates the PIE vector table with pointers
// to the shell ISR functions found in DSP28_DefaultIsr.c.
sInitPieVectTable();
//=======================Run in Flash=======================
#ifdef RunInFlash
pSourceAddr = (unsigned long *)RAM_FUNC_LOAD;
pDestAddr = (unsigned long *)RAM_FUNC_RUN;
for(i = 0; i < RAM_FUNC_LENGTH; i++)
{
*pDestAddr++ = *pSourceAddr++;
}
sInitFlash();
#endif
// Step 2. Initialize Event Manager registers for the specific application
sInitEV();
// Step 3. Initialize AD registers
sInitAdc();
// Step 4. Select GPIO for the device or for the specific application:
sInitGpio();
// Step 5. Initialize SCI registers
sInitSCI();
// Step 6. Initialize CAN registers
//sInitCAN();
sCanInitial(cPrioPara,eParallelCANParsing);
// Step 7. Initialize SPI registers
sInitSPI();
// Step 8. Initialize PIE vector table:
// The PIE vector table is initialized with pointers to shell Interrupt
// Service Routines (ISR). The shell routines are found in DSP28_DefaultIsr.c.
// Insert user specific ISR code in the appropriate shell ISR routine in
// the DSP28_DefaultIsr.c file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.XINT2 = &XINT2Interrupt;
PieVectTable.T1PINT = &PFCInterrupt;
PieVectTable.T1UFINT = &INVInterrupt;
PieVectTable.USER11 = &OSCtxSw;
PieVectTable.RXAINT = &SCIAReceiveInterrupt;
PieVectTable.TXAINT = &SCITransmitInterrupt;
//lg/040412 PieVectTable.CAPINT1 = &BypassZeroCrossInterrupt;
PieVectTable.CAPINT1 = &LineZeroCrossInterrupt;
PieVectTable.CAPINT2 = &SynchroZeroCrossInterrupt;//LC/040202
PieVectTable.CAPINT3 = &HostInterrupt;//lc/040510
//lg/040412 PieVectTable.CAPINT4 = &LineZeroCrossInterrupt;
PieVectTable.CAPINT4 = &BypassZeroCrossInterrupt;
PieVectTable.CAPINT5 = &InverterZeroCrossInterrupt;
PieVectTable.CAPINT6 = &OutputZeroCrossInterrupt;
PieVectTable.T4CINT = &TBASE_INT;
PieVectTable.ECAN1INTA = &CANInterrupt;
EDIS;
// enable EXT Interrupt 2 and Detect on rising edge
XIntruptRegs.XINT2CR.all = 5;
// Step 9. Initialize extern IO
sInitEXTIO();
// Disable and clear all CPU interrupts:
DINT;
IER = 0x0000;
IFR = 0x0000;
//Enbale PIE group 1 interrupt 5 for XINT2
PieCtrlRegs.PIEIER1.bit.INTx5 =1;
// Enable PIE group 2 interrupt 4 for T1PINT,interrupt 6 for T1UFINT
PieCtrlRegs.PIEIER2.bit.INTx4=1;
PieCtrlRegs.PIEIER2.bit.INTx6=1;
// Enalbe PIE group 3 interrupt 2 for T2CINT
// PieCtrlRegs.PIEIER3.bit.INTx2=1;
PieCtrlRegs.PIEIER3.bit.INTx5=1;
PieCtrlRegs.PIEIER3.bit.INTx6=1;
PieCtrlRegs.PIEIER3.bit.INTx7=1;
PieCtrlRegs.PIEIER5.bit.INTx2=1;
// Enable PIE group 5 interrupt 4,5,6 for CAPINT4,5,6
PieCtrlRegs.PIEIER5.bit.INTx5=1;
PieCtrlRegs.PIEIER5.bit.INTx6=1;
PieCtrlRegs.PIEIER5.bit.INTx7=1;
// Enable PIE group 9 interrupt 1 for SCIRXINTA, 5 for ECAN0INT,6 for ECAN1INT
PieCtrlRegs.PIEIER9.bit.INTx1=1;
PieCtrlRegs.PIEIER9.bit.INTx2=1;
PieCtrlRegs.PIEIER9.bit.INTx5=1;
PieCtrlRegs.PIEIER9.bit.INTx6=1;
sADCalibration();
hoAD_SW1=1;
hoAD_SW2=1;
//wInputModule=cSinglePhase; //ywt/061230A
wInputModule=cThreePhase; //ywt/061230A
//wOutputModule=cSinglePhase; //ywt/061230A
wOutputModule=cThreePhase; //ywt/061230A
// Enable CPU INT2 for T1PINT, INT4 for T3UFINT, INT5 for T4CINT,CAPINT4,5,6
// and INT 9 for SCIRXINTA,ECAN0INT,ECAN1INT
// IER |= (M_INT2 | M_INT3 | M_INT5 | M_INT9);
}
//---------------------------------------------------------------------------
// InitSysCtrl:
//---------------------------------------------------------------------------
// This function initializes the System Control registers to a known state.
//
void sInitSysCtrl(void)
{
unsigned int i;
EALLOW;
// On TMX samples, to get the best performance of on chip RAM blocks M0/M1/L0/L1/H0 internal
// control registers bit have to be enabled. The bits are in Device emulation registers.
DevEmuRegs.M0RAMDFT = 0x0300;
DevEmuRegs.M1RAMDFT = 0x0300;
DevEmuRegs.L0RAMDFT = 0x0300;
DevEmuRegs.L1RAMDFT = 0x0300;
DevEmuRegs.H0RAMDFT = 0x0300;
// Disable watchdog module
SysCtrlRegs.WDCR= 0x0068;
// Initalize PLL
SysCtrlRegs.PLLCR = 0xA;
// Wait for PLL to lock
for(i= 0; i< 5000; i++){}
// HISPCP/LOSPCP prescale register settings.
// high speed clock = SYSCLKOUT/1 (EVA,EVB,ADC)
SysCtrlRegs.HISPCP.all = 0x0000;
// low speed clock = SYSCLKOUT/4 (SCIA,SCIB,SPI,McBSP)
SysCtrlRegs.LOSPCP.all = 0x0002;
// Peripheral clock enables set for the selected peripherals.
SysCtrlRegs.PCLKCR.bit.EVAENCLK=1;
SysCtrlRegs.PCLKCR.bit.EVBENCLK=1;
SysCtrlRegs.PCLKCR.bit.SCIENCLKA=1;
SysCtrlRegs.PCLKCR.bit.SCIENCLKB=0;
SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;
SysCtrlRegs.PCLKCR.bit.SPIENCLK=1;
SysCtrlRegs.PCLKCR.bit.ECANENCLK=1;
SysCtrlRegs.PCLKCR.bit.ADCENCLK=1;
EDIS;
}
// This function initializes the Flash Control registers
// CAUTION
// This function MUST be executed out of RAM. Executing it
// out of OTP/Flash will yield unpredictable results
void sInitFlash(void)
{
EALLOW;
//Enable Flash Pipeline mode to improve performance
//of code executed from Flash.
FlashRegs.FOPT.bit.ENPIPE = 1;
// CAUTION
//Minimum waitstates required for the flash operating
//at a given CPU rate must be characterized by TI.
//Refer to the datasheet for the latest information.
//Set the Random Waitstate for the Flash
FlashRegs.FBANKWAIT.bit.RANDWAIT = 5;//lg/030905 5;
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