📄 registers.h
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// PRD, PRDH: Period register definitions:
struct PRD_REG {
unsigned int LSW;
unsigned int MSW;
};
union PRD_GROUP {
unsigned long all;
struct PRD_REG half;
};
//---------------------------------------------------------------------------
// CPU Timer Register File:
//
struct CPUTIMER_REGS {
union TIM_GROUP TIM; // Timer counter register
union PRD_GROUP PRD; // Period register
union TCR_REG TCR; // Timer control register
unsigned int rsvd1; // reserved
union TPR_REG TPR; // Timer pre-scale low
union TPRH_REG TPRH; // Timer pre-scale high
};
//---------------------------------------------------------------------------
// CPU Timer Support Variables:
//
struct CPUTIMER_VARS {
volatile struct CPUTIMER_REGS *RegsAddr;
unsigned long InterruptCount;
float CPUFreqInMHz;
float PeriodInUSec;
};
//---------------------------------------------------------------------------
// Device Emulation Register Bit Definitions:
//
// Device Configuration Register Bit Definitions
/*
INDEX: DeviceEMU_Registers ()
*/
struct DEVICECNF_BITS { // bits description
unsigned int rsvd1:3; // 2:0 reserved
unsigned int VMAPS:1; // 3 VMAP Status
unsigned int rsvd2:1; // 4 reserved
unsigned int XRSn:1; // 5 XRSn Signal Status
unsigned int rsvd3:10; // 15:6
unsigned int rsvd4:3; // 18:6
unsigned int ENPROT:1; // 19 Enable/Disable pipeline protection
unsigned int rsvd5:12; // 31:20 reserved
};
union DEVICECNF_REG {
unsigned long all;
struct DEVICECNF_BITS bit;
};
// Device ID Register Bit Definitions
struct DEVICEID_BITS { // bits description
unsigned int PARTID:16; // 15:0 Part ID
unsigned int REVID:16; // 31:16 Revision
};
union DEVICEID_REG {
unsigned long all;
struct DEVICEID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF;
union DEVICEID_REG DEVICEID;
unsigned int PROTSTART;
unsigned int PROTRANGE;
unsigned int rsvd[202];
unsigned int M0RAMDFT;
unsigned int M1RAMDFT;
unsigned int L0RAMDFT;
unsigned int L1RAMDFT;
unsigned int H0RAMDFT;
};
/* --------------------------------------------------- */
/* eCAN Control & Status Registers */
/* ----------------------------------------------------*/
/* eCAN Mailbox enable register (CANME) bit definitions */
/*
INDEX: eCAN_Registers ()
*/
/* --------------------------------------------------- */
/* eCAN Control & Status Registers */
/* ----------------------------------------------------*/
/* eCAN Mailbox enable register (CANME) bit definitions */
struct CANME_BITS { // bit description
unsigned int ME0:1; // 0 Enable Mailbox 0
unsigned int ME1:1; // 1 Enable Mailbox 1
unsigned int ME2:1; // 2 Enable Mailbox 2
unsigned int ME3:1; // 3 Enable Mailbox 3
unsigned int ME4:1; // 4 Enable Mailbox 4
unsigned int ME5:1; // 5 Enable Mailbox 5
unsigned int ME6:1; // 6 Enable Mailbox 6
unsigned int ME7:1; // 7 Enable Mailbox 7
unsigned int ME8:1; // 8 Enable Mailbox 8
unsigned int ME9:1; // 9 Enable Mailbox 9
unsigned int ME10:1; // 10 Enable Mailbox 10
unsigned int ME11:1; // 11 Enable Mailbox 11
unsigned int ME12:1; // 12 Enable Mailbox 12
unsigned int ME13:1; // 13 Enable Mailbox 13
unsigned int ME14:1; // 14 Enable Mailbox 14
unsigned int ME15:1; // 15 Enable Mailbox 15
unsigned int ME16:1; // 16 Enable Mailbox 16
unsigned int ME17:1; // 17 Enable Mailbox 17
unsigned int ME18:1; // 18 Enable Mailbox 18
unsigned int ME19:1; // 19 Enable Mailbox 19
unsigned int ME20:1; // 20 Enable Mailbox 20
unsigned int ME21:1; // 21 Enable Mailbox 21
unsigned int ME22:1; // 22 Enable Mailbox 22
unsigned int ME23:1; // 23 Enable Mailbox 23
unsigned int ME24:1; // 24 Enable Mailbox 24
unsigned int ME25:1; // 25 Enable Mailbox 25
unsigned int ME26:1; // 26 Enable Mailbox 26
unsigned int ME27:1; // 27 Enable Mailbox 27
unsigned int ME28:1; // 28 Enable Mailbox 28
unsigned int ME29:1; // 29 Enable Mailbox 29
unsigned int ME30:1; // 30 Enable Mailbox 30
unsigned int ME31:1; // 31 Enable Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANME_REG {
unsigned long all;
struct CANME_BITS bit;
};
/* eCAN Mailbox direction register (CANMD) bit definitions */
struct CANMD_BITS { // bit description
unsigned int MD0:1; // 0 0 -> Tx 1 -> Rx
unsigned int MD1:1; // 1 0 -> Tx 1 -> Rx
unsigned int MD2:1; // 2 0 -> Tx 1 -> Rx
unsigned int MD3:1; // 3 0 -> Tx 1 -> Rx
unsigned int MD4:1; // 4 0 -> Tx 1 -> Rx
unsigned int MD5:1; // 5 0 -> Tx 1 -> Rx
unsigned int MD6:1; // 6 0 -> Tx 1 -> Rx
unsigned int MD7:1; // 7 0 -> Tx 1 -> Rx
unsigned int MD8:1; // 8 0 -> Tx 1 -> Rx
unsigned int MD9:1; // 9 0 -> Tx 1 -> Rx
unsigned int MD10:1; // 10 0 -> Tx 1 -> Rx
unsigned int MD11:1; // 11 0 -> Tx 1 -> Rx
unsigned int MD12:1; // 12 0 -> Tx 1 -> Rx
unsigned int MD13:1; // 13 0 -> Tx 1 -> Rx
unsigned int MD14:1; // 14 0 -> Tx 1 -> Rx
unsigned int MD15:1; // 15 0 -> Tx 1 -> Rx
unsigned int MD16:1; // 16 0 -> Tx 1 -> Rx
unsigned int MD17:1; // 17 0 -> Tx 1 -> Rx
unsigned int MD18:1; // 18 0 -> Tx 1 -> Rx
unsigned int MD19:1; // 19 0 -> Tx 1 -> Rx
unsigned int MD20:1; // 20 0 -> Tx 1 -> Rx
unsigned int MD21:1; // 21 0 -> Tx 1 -> Rx
unsigned int MD22:1; // 22 0 -> Tx 1 -> Rx
unsigned int MD23:1; // 23 0 -> Tx 1 -> Rx
unsigned int MD24:1; // 24 0 -> Tx 1 -> Rx
unsigned int MD25:1; // 25 0 -> Tx 1 -> Rx
unsigned int MD26:1; // 26 0 -> Tx 1 -> Rx
unsigned int MD27:1; // 27 0 -> Tx 1 -> Rx
unsigned int MD28:1; // 28 0 -> Tx 1 -> Rx
unsigned int MD29:1; // 29 0 -> Tx 1 -> Rx
unsigned int MD30:1; // 30 0 -> Tx 1 -> Rx
unsigned int MD31:1; // 31 0 -> Tx 1 -> Rx
};
/* Allow access to the bit fields or entire register */
union CANMD_REG {
unsigned long all;
struct CANMD_BITS bit;
};
/* eCAN Transmit Request Set register (CANTRS) bit definitions */
struct CANTRS_BITS { // bit description
unsigned int TRS0:1; // 0 TRS for Mailbox 0
unsigned int TRS1:1; // 1 TRS for Mailbox 1
unsigned int TRS2:1; // 2 TRS for Mailbox 2
unsigned int TRS3:1; // 3 TRS for Mailbox 3
unsigned int TRS4:1; // 4 TRS for Mailbox 4
unsigned int TRS5:1; // 5 TRS for Mailbox 5
unsigned int TRS6:1; // 6 TRS for Mailbox 6
unsigned int TRS7:1; // 7 TRS for Mailbox 7
unsigned int TRS8:1; // 8 TRS for Mailbox 8
unsigned int TRS9:1; // 9 TRS for Mailbox 9
unsigned int TRS10:1; // 10 TRS for Mailbox 10
unsigned int TRS11:1; // 11 TRS for Mailbox 11
unsigned int TRS12:1; // 12 TRS for Mailbox 12
unsigned int TRS13:1; // 13 TRS for Mailbox 13
unsigned int TRS14:1; // 14 TRS for Mailbox 14
unsigned int TRS15:1; // 15 TRS for Mailbox 15
unsigned int TRS16:1; // 16 TRS for Mailbox 16
unsigned int TRS17:1; // 17 TRS for Mailbox 17
unsigned int TRS18:1; // 18 TRS for Mailbox 18
unsigned int TRS19:1; // 19 TRS for Mailbox 19
unsigned int TRS20:1; // 20 TRS for Mailbox 20
unsigned int TRS21:1; // 21 TRS for Mailbox 21
unsigned int TRS22:1; // 22 TRS for Mailbox 22
unsigned int TRS23:1; // 23 TRS for Mailbox 23
unsigned int TRS24:1; // 24 TRS for Mailbox 24
unsigned int TRS25:1; // 25 TRS for Mailbox 25
unsigned int TRS26:1; // 26 TRS for Mailbox 26
unsigned int TRS27:1; // 27 TRS for Mailbox 27
unsigned int TRS28:1; // 28 TRS for Mailbox 28
unsigned int TRS29:1; // 29 TRS for Mailbox 29
unsigned int TRS30:1; // 30 TRS for Mailbox 30
unsigned int TRS31:1; // 31 TRS for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRS_REG {
unsigned long all;
struct CANTRS_BITS bit;
};
/* eCAN Transmit Request Reset register (CANTRR) bit definitions */
struct CANTRR_BITS { // bit description
unsigned int TRR0:1; // 0 TRR for Mailbox 0
unsigned int TRR1:1; // 1 TRR for Mailbox 1
unsigned int TRR2:1; // 2 TRR for Mailbox 2
unsigned int TRR3:1; // 3 TRR for Mailbox 3
unsigned int TRR4:1; // 4 TRR for Mailbox 4
unsigned int TRR5:1; // 5 TRR for Mailbox 5
unsigned int TRR6:1; // 6 TRR for Mailbox 6
unsigned int TRR7:1; // 7 TRR for Mailbox 7
unsigned int TRR8:1; // 8 TRR for Mailbox 8
unsigned int TRR9:1; // 9 TRR for Mailbox 9
unsigned int TRR10:1; // 10 TRR for Mailbox 10
unsigned int TRR11:1; // 11 TRR for Mailbox 11
unsigned int TRR12:1; // 12 TRR for Mailbox 12
unsigned int TRR13:1; // 13 TRR for Mailbox 13
unsigned int TRR14:1; // 14 TRR for Mailbox 14
unsigned int TRR15:1; // 15 TRR for Mailbox 15
unsigned int TRR16:1; // 16 TRR for Mailbox 16
unsigned int TRR17:1; // 17 TRR for Mailbox 17
unsigned int TRR18:1; // 18 TRR for Mailbox 18
unsigned int TRR19:1; // 19 TRR for Mailbox 19
unsigned int TRR20:1; // 20 TRR for Mailbox 20
unsigned int TRR21:1; // 21 TRR for Mailbox 21
unsigned int TRR22:1; // 22 TRR for Mailbox 22
unsigned int TRR23:1; // 23 TRR for Mailbox 23
unsigned int TRR24:1; // 24 TRR for Mailbox 24
unsigned int TRR25:1; // 25 TRR for Mailbox 25
unsigned int TRR26:1; // 26 TRR for Mailbox 26
unsigned int TRR27:1; // 27 TRR for Mailbox 27
unsigned int TRR28:1; // 28 TRR for Mailbox 28
unsigned int TRR29:1; // 29 TRR for Mailbox 29
unsigned int TRR30:1; // 30 TRR for Mailbox 30
unsigned int TRR31:1; // 31 TRR for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTRR_REG {
unsigned long all;
struct CANTRR_BITS bit;
};
/* eCAN Transmit Acknowledge register (CANTA) bit definitions */
struct CANTA_BITS { // bit description
unsigned int TA0:1; // 0 TA for Mailbox 0
unsigned int TA1:1; // 1 TA for Mailbox 1
unsigned int TA2:1; // 2 TA for Mailbox 2
unsigned int TA3:1; // 3 TA for Mailbox 3
unsigned int TA4:1; // 4 TA for Mailbox 4
unsigned int TA5:1; // 5 TA for Mailbox 5
unsigned int TA6:1; // 6 TA for Mailbox 6
unsigned int TA7:1; // 7 TA for Mailbox 7
unsigned int TA8:1; // 8 TA for Mailbox 8
unsigned int TA9:1; // 9 TA for Mailbox 9
unsigned int TA10:1; // 10 TA for Mailbox 10
unsigned int TA11:1; // 11 TA for Mailbox 11
unsigned int TA12:1; // 12 TA for Mailbox 12
unsigned int TA13:1; // 13 TA for Mailbox 13
unsigned int TA14:1; // 14 TA for Mailbox 14
unsigned int TA15:1; // 15 TA for Mailbox 15
unsigned int TA16:1; // 16 TA for Mailbox 16
unsigned int TA17:1; // 17 TA for Mailbox 17
unsigned int TA18:1; // 18 TA for Mailbox 18
unsigned int TA19:1; // 19 TA for Mailbox 19
unsigned int TA20:1; // 20 TA for Mailbox 20
unsigned int TA21:1; // 21 TA for Mailbox 21
unsigned int TA22:1; // 22 TA for Mailbox 22
unsigned int TA23:1; // 23 TA for Mailbox 23
unsigned int TA24:1; // 24 TA for Mailbox 24
unsigned int TA25:1; // 25 TA for Mailbox 25
unsigned int TA26:1; // 26 TA for Mailbox 26
unsigned int TA27:1; // 27 TA for Mailbox 27
unsigned int TA28:1; // 28 TA for Mailbox 28
unsigned int TA29:1; // 29 TA for Mailbox 29
unsigned int TA30:1; // 30 TA for Mailbox 30
unsigned int TA31:1; // 31 TA for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANTA_REG {
unsigned long all;
struct CANTA_BITS bit;
};
/* eCAN Transmit Abort Acknowledge register (CANAA) bit definitions */
struct CANAA_BITS { // bit description
unsigned int AA0:1; // 0 AA for Mailbox 0
unsigned int AA1:1; // 1 AA for Mailbox 1
unsigned int AA2:1; // 2 AA for Mailbox 2
unsigned int AA3:1; // 3 AA for Mailbox 3
unsigned int AA4:1; // 4 AA for Mailbox 4
unsigned int AA5:1; // 5 AA for Mailbox 5
unsigned int AA6:1; // 6 AA for Mailbox 6
unsigned int AA7:1; // 7 AA for Mailbox 7
unsigned int AA8:1; // 8 AA for Mailbox 8
unsigned int AA9:1; // 9 AA for Mailbox 9
unsigned int AA10:1; // 10 AA for Mailbox 10
unsigned int AA11:1; // 11 AA for Mailbox 11
unsigned int AA12:1; // 12 AA for Mailbox 12
unsigned int AA13:1; // 13 AA for Mailbox 13
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