📄 gpio.c
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/*********************************************************************
* File: Gpio.c *
* Description: Contains GPIO functions used in the TEC application. *
* DSP: TMS320F2812 *
* Author: David M. Alter *
* Function List: InitGpio() *
* History: *
* 11/05/02 - Original, based on DSP28 header files v0.58 (D. Alter)*
* Notes: none *
*********************************************************************/
/*********************************************************************
* THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR *
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* YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS *
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* *
* Unless otherwise stated, the Program written and copyrighted *
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* only under TI's copyright in the Program, use and modify the *
* Program without any charge or restriction. You may *
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* copy of this license to the third party and the third party *
* agrees to these terms by its first use of the Program. You *
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* You acknowledge and agree that the Program contains *
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* copyright notice included in the Program. TI reserves all *
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* You may not use the Program in non-TI devices. *
*********************************************************************/
#include "Device.h"
/*********************************************************************
* Function: InitGpio() *
* Description: Initializes the shared I/O pin mux control registers *
* DSP: TMS320F2812 *
* Author: David M. Alter *
* Include files: none *
* Function Prototype: void InitGpio(void) *
* Useage: InitGpio(); *
* Input Parameters: none *
* Return Value: none *
* Notes: none *
*********************************************************************/
void InitGpio(void)
{
/*** Enable EALLOW protected register access ***/
asm(" EALLOW");
/*** Group A pins ***/
GpioMuxRegs.GPAQUAL.all = 0x0000; // Input qualifier disabled
GpioMuxRegs.GPADIR.all = 0x0000; // All group A GPIO are inputs
GpioMuxRegs.GPAMUX.all = 0x0003;
/*
bit 15 0: 0=GPIOA15, 1=C3TRIP
bit 14 0: 0=GPIOA14, 1=C2TRIP
bit 13 0: 0=GPIOA13, 1=C1TRIP
bit 12 0: 0=GPIOA12, 1=TCLKINA
bit 11 0: 0=GPIOA11, 1=TDIRA
bit 10 0: 0=GPIOA10, 1=CAP3_QEPI1
bit 9 0: 0=GPIOA9, 1=CAP2_QEP2
bit 8 0: 0=GPIOA8, 1=CAP1_QEP1
bit 7 0: 0=GPIOA7, 1=T2PWM_T2CMP
bit 6 0: 0=GPIOA6, 1=T1PWM_T1CMP
bit 5 0: 0=GPIOA5, 1=PWM6
bit 4 0: 0=GPIOA4, 1=PWM5
bit 3 0: 0=GPIOA3, 1=PWM4
bit 2 0: 0=GPIOA2, 1=PWM3
bit 1 1: 0=GPIOA1 1=PWM2
bit 0 1: 0=GPIOA0, 1=PWM1
*/
/*** Group B pins ***/
GpioMuxRegs.GPBQUAL.all = 0x0000; // Input qualifier disabled
GpioMuxRegs.GPBDIR.all = 0x0000; // All group B GPIO are inputs
GpioMuxRegs.GPBMUX.all = 0x0000;
/*
bit 15 0: 0=GPIOB15, 1=C6TRIP
bit 14 0: 0=GPIOB14, 1=C5TRIP
bit 13 0: 0=GPIOB13, 1=C4TRIP
bit 12 0: 0=GPIOB12, 1=TCLKINB
bit 11 0: 0=GPIOB11, 1=TDIRB
bit 10 0: 0=GPIOB10, 1=CAP6_QEPI2
bit 9 0: 0=GPIOB9, 1=CAP5_QEP5
bit 8 0: 0=GPIOB8, 1=CAP4_QEP4
bit 7 0: 0=GPIOB7, 1=T4PWM_T4CMP
bit 6 0: 0=GPIOB6, 1=T3PWM_T3CMP
bit 5 0: 0=GPIOB5, 1=PWM12
bit 4 0: 0=GPIOB4, 1=PWM11
bit 3 0: 0=GPIOB3, 1=PWM10
bit 2 0: 0=GPIOB2, 1=PWM9
bit 1 0: 0=GPIOB1 1=PWM8
bit 0 0: 0=GPIOB0, 1=PWM7
*/
/*** Group D pins ***/
GpioMuxRegs.GPDQUAL.all=0x0000; // Input qualifier disabled
GpioMuxRegs.GPDDIR.all = 0x0000; // All group D GPIO are inputs
GpioMuxRegs.GPDMUX.all = 0x0000;
/*
bit 15 0: 0=GPIOD15, 1=reserved
bit 14 0: 0=GPIOD14, 1=reserved
bit 13 0: 0=GPIOD13, 1=reserved
bit 12 0: 0=GPIOD12, 1=reserved
bit 11 0: 0=GPIOD11, 1=reserved
bit 10 0: 0=GPIOD10, 1=reserved
bit 9 0: 0=GPIOD9, 1=reserved
bit 8 0: 0=GPIOD8, 1=reserved
bit 7 0: 0=GPIOD7, 1=reserved
bit 6 0: 0=GPIOD6, 1=T4TRIP
bit 5 0: 0=GPIOD5, 1=T3CTRIP_PDPINTB
bit 4 0: 0=GPIOD4, 1=reserved
bit 3 0: 0=GPIOD3, 1=reserved
bit 2 0: 0=GPIOD2, 1=reserved
bit 1 0: 0=GPIOD1 1=T2CTRIP
bit 0 0: 0=GPIOD0, 1=T1CTRIP_PDPINTA
*/
/*** Group E pins ***/
GpioMuxRegs.GPEQUAL.all = 0x0000; // Input qualifier disabled
GpioMuxRegs.GPEDIR.all = 0x0000; // All group E GPIO are inputs
GpioMuxRegs.GPEMUX.all = 0x0000;
/*
bit 15 0: 0=GPIOE15, 1=reserved
bit 14 0: 0=GPIOE14, 1=reserved
bit 13 0: 0=GPIOE13, 1=reserved
bit 12 0: 0=GPIOE12, 1=reserved
bit 11 0: 0=GPIOE11, 1=reserved
bit 10 0: 0=GPIOE10, 1=reserved
bit 9 0: 0=GPIOE9, 1=reserved
bit 8 0: 0=GPIOE8, 1=reserved
bit 7 0: 0=GPIOE7, 1=reserved
bit 6 0: 0=GPIOE6, 1=reserved
bit 5 0: 0=GPIOE5, 1=reserved
bit 4 0: 0=GPIOE4, 1=reserved
bit 3 0: 0=GPIOE3, 1=reserved
bit 2 0: 0=GPIOE2, 1=XNMI_XINT13
bit 1 0: 0=GPIOE1 1=XINT2_ADCSOC
bit 0 0: 0=GPIOE0, 1=XINT1_XBIO
*/
/*** Group F pins ***/
GpioMuxRegs.GPFDIR.all = 0x0000; // All group F GPIO are inputs
GpioMuxRegs.GPFMUX.all = 0x0000;
/*
bit 15 0: 0=reserved, 1=reserved
bit 14 0: 0=GPIOF14, 1=XF
bit 13 0: 0=GPIOF13, 1=MDR
bit 12 0: 0=GPIOF12, 1=MDX
bit 11 0: 0=GPIOF11, 1=MFSR
bit 10 0: 0=GPIOF10, 1=MFSX
bit 9 0: 0=GPIOF9, 1=MCLKR
bit 8 0: 0=GPIOF8, 1=MCLKX
bit 7 0: 0=GPIOF7, 1=CANRX
bit 6 0: 0=GPIOF6, 1=CANTX
bit 5 0: 0=GPIOF5, 1=SCIRXDA
bit 4 0: 0=GPIOF4, 1=SCITXDA
bit 3 0: 0=GPIOF3, 1=SPISTE
bit 2 0: 0=GPIOF2, 1=SPICLK
bit 1 0: 0=GPIOF1 1=SPISOMI
bit 0 0: 0=GPIOF0, 1=SPISIMO
*/
/*** Group G pins ***/
GpioMuxRegs.GPGDIR.all = 0x0000; // All group G GPIO are inputs
GpioMuxRegs.GPGDIR.all = 0x0000;
/*
bit 15 0: 0=GPIOG15, 1=reserved
bit 14 0: 0=GPIOG14, 1=reserved
bit 13 0: 0=GPIOG13, 1=reserved
bit 12 0: 0=GPIOG12, 1=reserved
bit 11 0: 0=GPIOG11, 1=reserved
bit 10 0: 0=GPIOG10, 1=reserved
bit 9 0: 0=GPIOG9, 1=reserved
bit 8 0: 0=GPIOG8, 1=reserved
bit 7 0: 0=GPIOG7, 1=reserved
bit 6 0: 0=GPIOG6, 1=reserved
bit 5 0: 0=GPIOG5, 1=SCIRXDB
bit 4 0: 0=GPIOG4, 1=SCITXDB
bit 3 0: 0=GPIOG3, 1=reserved
bit 2 0: 0=GPIOG2, 1=reserved
bit 1 0: 0=GPIOG1 1=reserved
bit 0 0: 0=GPIOG0, 1=reserved
*/
/*** Disable EALLOW protected register access ***/
asm(" EDIS");
} //end InitGpio()
/*** end of file *****************************************************/
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