📄 main.lst
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main.asm Assembled with CASM08Z 3/18/2003 3:17:52 PM PAGE 1
1 loadall
2
3 ;/**************************************************
***************************/
4 ;/* PROJECT : Mosport State Machine Mimic MODULE
: MAIN */
5 ;/**************************************************
***************************/
6 ; Initial version: Jeff Burgess
7
0000 8 RAMStart EQU $0080
0000 9 RomStart EQU $7880
0000 10 VectorStart EQU $FFF2
11
12
0000 13 $Include 'hardef.h'
14 ** hardef.h
15 ** Tango 3 I/O assignments
0000 16 Band EQU 0 ; pb0
0000 17 Enable EQU 1 ; pb1
0000 18 DATA_RF EQU 2 ; pb2
0000 19 UP_CLOCK EQU 3 ; pb3
20
0000 21 Mode EQU 7 ; PA7 **Important:
porta!!! NOT portb!!!
0000 22 $Include 'rk2regs.h'
23 ; 68HC908RK2 Equates
24
0000 25 PTA EQU $0000 ; Ports and data
direction
0000 26 PORTA EQU $0000
0000 27 PTB EQU $0001
0000 28 PORTB EQU $0001
0000 29 DDRA EQU $0004
0000 30 DDRB EQU $0005
31
0000 32 INTKBSR EQU $001A ; IRQ & Keyboard
0000 33 IKBSR EQU $001A
0000 34 INTKBIER EQU $001B
0000 35 IKBIER EQU $001B
36
0000 37 CONFIG EQU $001F ; System configurati
on register
38
0000 39 TSC EQU $0020 ; Timer
0000 40 TCNTH EQU $0021
0000 41 TCNTL EQU $0022
0000 42 TMODH EQU $0023
0000 43 TMODL EQU $0024
0000 44 TSC0 EQU $0025
0000 45 TCH0H EQU $0026
0000 46 TCH0L EQU $0027
0000 47 TSC1 EQU $0028
0000 48 TCH1H EQU $0029
0000 49 TCH1L EQU $002A
50
0000 51 ICGCR EQU $0036 ; Internal Clock
Generator
main.asm Assembled with CASM08Z 3/18/2003 3:17:52 PM PAGE 2
0000 52 ICGMR EQU $0037
0000 53 ICGTR EQU $0038
0000 54 ICDVR EQU $0039
0000 55 ICGDSR EQU $003A
56
0000 57 SBSR EQU $FE00 ; SIM Module
0000 58 SRSR EQU $FE01
0000 59 SBFCR EQU $FE02
60
0000 61 FLCR EQU $FE08 ; Flash control
0000 62 FLBPR EQU $FFF0
63
0000 64 BRKH EQU $FE0C ; Break control
0000 65 BRKL EQU $FE0D
0000 66 BSCR EQU $FE0E
67
0000 68 LVISR EQU $FE0F ; LVI Status
register
0000 69 LOWV EQU !5
0000 70 LVIOUT EQU !7
71
0000 72 COPCTL EQU $FFFF ; COP control
register
73
74 ;(C)opywrite P&E Microcomputer Systems, 1998
75 ; You may use this code freely as long as this
copyright notice
76 ; is included.
0000 77 $Include 'rom1.h'
78 ;/**************************************************
***************************/
79 ;/* PROJECT : RF key demonstrator (ASK or FSK)
*/
80 ;/* constant file
*/
81 ;/**************************************************
***************************/
82
83 ;/* Protocol */
84
85 ; nb_wake_up_bit EQU !40 ; =3*10+1+8-4(alre
ady in header &F6) + stroke(=5)
0000 86 nb_wake_up_bit EQU !32 ; =3*10+1-4(already
in header &FB86) + stroke(=5)
87 ; nb_wake_up_bit EQU !32 ; =3*10+1+8-12(alr
eady in preamble &FFF6) + stroke(=5)
88 ; nb_wake_up_bit equ !08 ; Use this if
Cagc = 10nF (FSK 9600 bauds only)
89
90 ;***************************************************
***************************
0000 91 PREAMBLE EQU $FB86 ; End of Tone + ID
(B8) + Header (for using Romeo2 SPI)
0000 92 DEVICE_ID EQU $7800 ;Location of the
Device ID in ROM
93 ;***************************************************
***************************
94
main.asm Assembled with CASM08Z 3/18/2003 3:17:52 PM PAGE 3
0000 95 wait_0_2ms EQU !400 ;
0000 96 wait_0_5ms EQU !1000 ;
0000 97 wait_0_8ms EQU !1600 ; for L90J pressure
sense
0000 98 wait_1ms EQU !2000 ; = 1 ms
0000 99 wait_1_8ms EQU !381 ; = 1.8 ms for
Tango3 (434 MHz)
100
101 ;/* Transmission Timer Clock Generator
*/
102 ;/* This is the section that must be modified when
the crystal is changed. */
103 ;/* You will also have to clear TSC[2:0] during
transmission (see emis1.asm) */
104
105 ;/* ~9600 bauds using MCU clock for timer (not as
accurate over temperature) */
106 ; UHF_period EQU !200 ; =2MHz/10000bauds
107 ; UHF_Duty_Cycle EQU !100 ; =0.5*UHF_period
108
109 ;/* use of DATACLK at 9600 bauds, 434 MHz*/
0000 110 UHF_period EQU !20 ; = 212kHz/9600
bauds
0000 111 UHF_Duty_Cycle EQU !10 ; = 50%
112
113 ;/* use of DATACLK at 9600 bauds, 315 MHz*/
114 ; UHF_period EQU !16 ; = 154kHz/9600
bauds
115 ; UHF_Duty_Cycle EQU !8 ; = 50%
116
117 ;/* use of DATACLK at 1200 bauds, 434 MHz:*/
118 ; UHF_period_park EQU !176 ; = 212kHz/120
0 bauds
119 ; UHF_Duty_Cycle_park EQU !88 ; = 50%
120
121 ;/* use of DATACLK at 1200 bauds, 315 MHz:*/
122 ; UHF_period_park EQU !128 ; = 154kHz/120
0 bauds
123 ; UHF_Duty_Cycle_park EQU !64 ; = 50%
124
125 ;/* FLASH */
126
0000 127 RDVRRNG EQU $F000
0000 128 PRGRNGE EQU $F003
0000 129 ERARNGE EQU $F006
0000 130 $Include 'daytona_hardware_def_ADOR.h'
131 ** daytona_hardware_def.h
132 ** Daytona I/O assignments
133 ** Rev 0.0
134 ** 24 April 2001
135
136 * Mode Control pins *
137
0000 138 S1Vpp EQU 1 ; PTA1
0000 139 S0 EQU 2 ; PTA2
140
141 * Digital Data Output Pin *
142
main.asm Assembled with CASM08Z 3/18/2003 3:17:52 PM PAGE 4
0000 143 DOUT_BAR EQU 3 ; PTA3
0000 144 DOUTb EQU 3
145
146 * Data Clock Pin *
147
0000 148 DCLK EQU 4 ; PTA4
149
150 * Serial Data In Pin *
151
0000 152 SDATA EQU 5 ; PTA5
0000 153 DDATA EQU 5
154 ; Daytona
Hardware Pin Definitions
155
0088 156 org RAMStart+8
0088 157 $Include 'ram.h'
158 ;/**************************************************
***************************/
159 ;/* PROJECT : RF key demonstrator (ASK or FSK)
*/
160 ;/* Variable file
*/
161 ;/* Modified by Jeff Burgess
*/
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