m68328.h

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#define M328_UARTMISC2	(M328BASE+0x918)
#define M328_UNIPR2		(M328BASE+0x91A)
/* UHMARK exisits only in VZ UART-2 so a straight definition suffices */
#define M328_UHMARK2	(M328BASE+0x91C)		/* FIFO Half Mark Register */
/*** ... ADD VZ-013 ***/

#elif defined(EZ328)
#define M328_USTCNT     (M328BASE+0x900)        /* Status/Control Reg */
#define M328_UBAUD      (M328BASE+0x902)        /* Baud Control Reg */
#define M328_UARTRX     (M328BASE+0x904)        /* Rx Reg */
#define M328_UARTTX     (M328BASE+0x906)        /* Tx Reg */
#define M328_UARTMISC   (M328BASE+0x908)        /* Misc Reg */
#define M328_UNIPR      (M328BASE+0x90A)        /* Non-integer prescalar Reg *//*** ADD CE-004 ***//*** MOD CE-013 ***/

#else
#error /* Undefined compile flag - platform */
#endif

/* LCDC Registers */
#define M328_LSSA       (M328BASE+0xA00)        /* Screen Start Addr Reg */
#define M328_LVPW       (M328BASE+0xA05)        /* Virtual Page Width Reg */
#define M328_LXMAX      (M328BASE+0xA08)        /* Screen Width Reg */
#define M328_LYMAX      (M328BASE+0xA0A)        /* Screen Height Reg */
#define M328_LCXP       (M328BASE+0xA18)        /* Cursor X Position */
#define M328_LCYP       (M328BASE+0xA1A)        /* Cursor Y Position */
#define M328_LCWCH      (M328BASE+0xA1C)        /* Cursor Width & Height Reg */
#define M328_LBLKC      (M328BASE+0xA1F)        /* Blink Control Reg */
#define M328_LPICF      (M328BASE+0xA20)        /* Panel Interface Config Reg */
#define M328_LPOLCF     (M328BASE+0xA21)        /* Polarity Config Reg */
#define M328_LACDRC     (M328BASE+0xA23)        /* ACD (M) Rate Control Reg */
#define M328_LPXCD      (M328BASE+0xA25)        /* Pixel Clock Divider Reg */
#define M328_LCKCON     (M328BASE+0xA27)        /* Clocking Control Reg */
#define M328_LRRA       (M328BASE+0xA29)        /* Refresh Rate Adjustment Reg */
#define M328_LLMLR      (M328BASE+0xA2B)        /* Line Buffer Mininum Level Reg */
#define M328_LPOSR      (M328BASE+0xA2D)        /* Panning Offset Reg */
#define M328_LFRCM      (M328BASE+0xA31)        /* Frame Rate Control Mod Reg */
#define M328_LGPMR      (M328BASE+0xA33)        /* Gray Palette Mapping Reg *//*** MOD EL-111 ***/
#define M328_LPWMR      (M328BASE+0xA36)        /* Contrast control PWM Reg */

/* RTC Registers */
#define M328_RTCHMSR    (M328BASE+0xB00)        /* Hrs Mins Secs Reg */
#define M328_RTCHR      (M328BASE+0xB00)        /* Hrs Reg */
#define M328_RTCMR      (M328BASE+0xB01)        /* Mins Reg */
#define M328_RTCSR      (M328BASE+0xB03)        /* Secs Reg */
#define M328_RTCALM0R   (M328BASE+0xB04)        /* Alarm Register 0 */
#define M328_RTCCTL     (M328BASE+0xB0C)        /* Control Reg */
#define M328_RTCISR     (M328BASE+0xB0E)        /* Interrupt Status Reg */
#define M328_RTCIENR    (M328BASE+0xB10)        /* Interrupt Enable Reg */
#define M328_RSTPWCH    (M328BASE+0xB12)        /* Stopwatch Minutes */
#define M328_RTCDAY	(M328BASE+0xB1A)	/* Day register */
#define M328_RTCDAYAL	(M328BASE+0xB1C)	/* Day Alarm register */

/* New DRAM Registers supported*/
#define M328_DRAMMC     (M328BASE+0xC00)        /* Memory Config Reg */
#define M328_DRAMC      (M328BASE+0xC02)        /* Control Reg */

/* New Emulation Register supported */
#define M328_ICEMACR    (M328BASE+0xD00)        /* Address Compare Reg */
#define M328_ICEMAMR    (M328BASE+0xD04)        /* Address Mask Reg */
#define M328_ICEMCCR    (M328BASE+0xD08)        /* Control Compare Reg */
#define M328_ICEMCMR    (M328BASE+0xD0A)        /* Control Mask Reg */
#define M328_ICEMCR     (M328BASE+0xD0C)        /* Control Reg */
#define M328_ICEMSR     (M328BASE+0xD0E)        /* Control Status */

#else
#error /* Undefined compile flag - platform */

					/* CS Group Base Registers */
#define	M328_GRPBASEA	(M328BASE+0x100)	
#define	M328_GRPBASEB	(M328BASE+0x102)
#define	M328_GRPBASEC	(M328BASE+0x104)
#define	M328_GRPBASED	(M328BASE+0x106)
					/* CS Group Mask Registers */
#define	M328_GRPMASKA	(M328BASE+0x108)
#define	M328_GRPMASKB	(M328BASE+0x10A)
#define	M328_GRPMASKC	(M328BASE+0x10C)
#define	M328_GRPMASKD	(M328BASE+0x10E)
					/* Group A CS Registers */
#define	M328_CSA0	(M328BASE+0x110)
#define	M328_CSA1	(M328BASE+0x114)
#define	M328_CSA2	(M328BASE+0x118)
#define	M328_CSA3	(M328BASE+0x11C)
                                        /* Group B CS Registers */
#define M328_CSB0       (M328BASE+0x120)
#define	M328_CSB1	(M328BASE+0x124)
#define	M328_CSB2	(M328BASE+0x128)
#define	M328_CSB3	(M328BASE+0x12C)
					/* Group C CS Registers */
#define	M328_CSC0	(M328BASE+0x130)
#define	M328_CSC1	(M328BASE+0x134)
#define	M328_CSC2	(M328BASE+0x138)
#define	M328_CSC3	(M328BASE+0x13C)
					/* Group D CS Registers */
#define	M328_CSD0	(M328BASE+0x140)
#define	M328_CSD1	(M328BASE+0x144)
#define	M328_CSD2	(M328BASE+0x148)
#define	M328_CSD3	(M328BASE+0x14C)

/* PLL Registers */
#define	M328_PLLCR	(M328BASE+0x200)	/* Control Reg */
#define	M328_PLLFSR	(M328BASE+0x202)	/* Freq Select Reg */
#define	M328_PLLTSR	(M328BASE+0x204)	/* Test Reg */

/* Power Control Registers */
#define	M328_PCTLR	(M328BASE+0x206)	/* Control Reg */

/* Interrupt Registers */
#define	M328_IVR	(M328BASE+0x300)	/* Interrupt Vector Reg */
#define	M328_ICR	(M328BASE+0x302)	/* Interrupt Control Reg */
#define	M328_IMR	(M328BASE+0x304)	/* Interrupt Mask Reg */
#define	M328_IWR	(M328BASE+0x308)	/* Wakeup Enable Reg */
#define	M328_ISR	(M328BASE+0x30C)	/* Interrupt Status Reg */
#define	M328_IPR	(M328BASE+0x310)	/* Interrupt Pending Reg */

/* PIO Registers */
					/* Port A Registers */
#define	M328_PADIR	(M328BASE+0x400)	/* Direction Reg */
#define	M328_PADATA	(M328BASE+0x401)	/* Data Reg */
#define	M328_PASEL	(M328BASE+0x403)	/* Select Reg */
					/* Port B Registers */
#define	M328_PBDIR	(M328BASE+0x408)	/* Direction Reg */
#define	M328_PBDATA	(M328BASE+0x409)	/* Data Reg */
#define	M328_PBSEL	(M328BASE+0x40B)	/* Select Reg */
					/* Port C Registers */
#define	M328_PCDIR	(M328BASE+0x410)	/* Direction Reg */
#define	M328_PCDATA	(M328BASE+0x411)	/* Data Reg */
#define	M328_PCSEL	(M328BASE+0x413)	/* Select Reg */
					/* Port D Registers */
#define	M328_PDDIR	(M328BASE+0x418)	/* Direction Reg */
#define	M328_PDDATA	(M328BASE+0x419)	/* Data Reg */
#define	M328_PDPUEN	(M328BASE+0x41A)	/* Pullup Enable Reg */
#define	M328_PDPOL	(M328BASE+0x41C)	/* Polarity Reg */
#define	M328_PDIRQEN	(M328BASE+0x41D)	/* IRQ Enable Reg */
#define	M328_PDIRQEDGE	(M328BASE+0x41F)	/* IRQ Edge Reg */
					/* Port E Registers */
#define	M328_PEDIR	(M328BASE+0x420)	/* Direction Reg */
#define	M328_PEDATA	(M328BASE+0x421)	/* Data Reg */
#define	M328_PESEL	(M328BASE+0x423)	/* Select Reg */
					/* Port F Registers */
#define	M328_PFDIR	(M328BASE+0x428)	/* Direction Reg */
#define	M328_PFDATA	(M328BASE+0x429)	/* Data Reg */
#define	M328_PFSEL	(M328BASE+0x42B)	/* Select Reg */
					/* Port G Registers */
#define	M328_PGDIR	(M328BASE+0x430)	/* Direction Reg */
#define	M328_PGDATA	(M328BASE+0x431)	/* Data Reg */
#define	M328_PGPUEN	(M328BASE+0x432)	/* Pullup Enable Reg */
#define	M328_PGSEL	(M328BASE+0x433)	/* Select Reg */
					/* Port J Registers */
#define	M328_PJDIR	(M328BASE+0x438)	/* Direction Reg */
#define	M328_PJDATA	(M328BASE+0x439)	/* Data Reg */
#define	M328_PJSEL	(M328BASE+0x43B)	/* Select Reg */
					/* Port K Registers */
#define	M328_PKDIR	(M328BASE+0x440)	/* Direction Reg */
#define	M328_PKDATA	(M328BASE+0x441)	/* Data Reg */
#define	M328_PKSEL	(M328BASE+0x443)	/* Select Reg */
					/* Port M Registers */
#define	M328_PMDIR	(M328BASE+0x448)	/* Direction Reg */
#define	M328_PMDATA	(M328BASE+0x449)	/* Data Reg */
#define	M328_PMPUEN	(M328BASE+0x44A)	/* Pullup Enable Reg */
#define	M328_PMSEL	(M328BASE+0x44B)	/* Select Reg */

/* PWM Registers */
#define	M328_PWMC	(M328BASE+0x500)	/* Control Reg */
#define	M328_PWMP	(M328BASE+0x502)	/* Period Reg */
#define	M328_PWMW	(M328BASE+0x504)	/* Width Reg */
#define	M328_PWMCNT	(M328BASE+0x506)	/* Counter */

/* Timer Registers */
					/* Timer 1 Registers */
#define	M328_TIMER1	(M328BASE+0x600)	/* Control Reg */
#define	M328_TCTL1	(M328BASE+0x600)	/* Control Reg */
#define	M328_TPRER1	(M328BASE+0x602)	/* Prescalar Reg */
#define	M328_TCMP1	(M328BASE+0x604)	/* Compare Reg */
#define	M328_TCR1	(M328BASE+0x606)	/* Capture Reg */
#define	M328_TCN1	(M328BASE+0x608)	/* Counter */
#define	M328_TSTAT1	(M328BASE+0x60A)	/* Status Reg */
					/* Timer 2 Registers */
#define	M328_TIMER2	(M328BASE+0x60C)	/* Control Reg */
#define	M328_TCTL2	(M328BASE+0x60C)	/* Control Reg */
#define	M328_TPRER2	(M328BASE+0x60E)	/* Prescalar Reg */
#define	M328_TCMP2	(M328BASE+0x610)	/* Compare Reg */
#define	M328_TCR2	(M328BASE+0x612)	/* Capture Reg */
#define	M328_TCN2	(M328BASE+0x614)	/* Counter */
#define	M328_TSTAT2	(M328BASE+0x616)	/* Status Reg */

/* Watchdog Registers */
#define	M328_WDG	(M328BASE+0x618)	/* WatchDog */
#define	M328_WCR	(M328BASE+0x618)	/* Control Reg */
#define	M328_WRR	(M328BASE+0x61A)	/* Reference Reg */
#define	M328_WCN	(M328BASE+0x61C)	/* Counter */

/* SPI Registers */
					/* SPI Slave Registers */
#define	M328_SPISR	(M328BASE+0x700)	/* SPIS Reg */
					/* SPI Master Registers */
#define	M328_SPIMDATA	(M328BASE+0x800)	/* Control/Status Reg */
#define	M328_SPIMCONT	(M328BASE+0x802)	/* Data Reg */

/* UART Registers */
#define	M328_USTCNT	(M328BASE+0x900)	/* Status Control Reg */
#define	M328_UBAUD	(M328BASE+0x902)	/* Baud Control Reg */
#define	M328_UARTRX	(M328BASE+0x904)	/* Rx Reg */
#define	M328_UARTTX	(M328BASE+0x906)	/* Tx Reg */
#define	M328_UARTMISC	(M328BASE+0x908)	/* Misc Reg */

/* LCDC Registers */
#define	M328_LSSA	(M328BASE+0xA00)	/* Screen Start Addr Reg */
#define	M328_LVPW	(M328BASE+0xA05)	/* Virtual Page Width Reg */
#define	M328_LXMAX	(M328BASE+0xA08)	/* Screen Width Reg */
#define	M328_LYMAX	(M328BASE+0xA0A)	/* Screen Height Reg */
#define	M328_LCXP	(M328BASE+0xA18)	/* Cursor X Position */
#define	M328_LCYP	(M328BASE+0xA1A)	/* Cursor Y Position */
#define	M328_LCWCH	(M328BASE+0xA1C)	/* Cursor Width & Height Reg */
#define	M328_LBLKC	(M328BASE+0xA1F)	/* Blink Control Reg */
#define	M328_LPICF	(M328BASE+0xA20)	/* Panel Interface Config Reg */
#define	M328_LPOLCF	(M328BASE+0xA21)	/* Polarity Config Reg */
#define	M328_LACDRC	(M328BASE+0xA23)	/* ACD (M) Rate Control Reg */
#define	M328_LPXCD	(M328BASE+0xA25)	/* Pixel Clock Divider Reg */
#define	M328_LCKCON	(M328BASE+0xA27)	/* Clocking Control Reg */
#define	M328_LLBAR	(M328BASE+0xA29)	/* Last Buffer Addr Reg */
#define	M328_LOTCR	(M328BASE+0xA2B)	/* Octet Terminal Count Reg */
#define	M328_LPOSR	(M328BASE+0xA2D)	/* Panning Offset Reg */
#define	M328_LFRCM	(M328BASE+0xA31)	/* Frame Rate Control Mod Reg */
#define	M328_LGPMR	(M328BASE+0xA32)	/* Gray Palette Mapping Reg */
#define	M328_LIRQR	(M328BASE+0xA34)	/* Interrupt Control Reg */

/* RTC Registers */
#define	M328_RTCHMSR	(M328BASE+0xB00)	/* Hrs Mins Secs Reg */
#define	M328_RTCHR	(M328BASE+0xB00)	/* Hrs Reg */
#define	M328_RTCMR	(M328BASE+0xB01)	/* Mins Reg */
#define	M328_RTCSR	(M328BASE+0xB03)	/* Secs Reg */
#define	M328_RTCALM0R	(M328BASE+0xB04)	/* Alarm Register 0 */
#define	M328_RTCALM1R	(M328BASE+0xB08)	/* Alarm Register 1 */
#define	M328_RTCCTL	(M328BASE+0xB0C)	/* Control Reg */
#define	M328_RTCISR	(M328BASE+0xB0E)	/* Interrupt Status Reg */
#define	M328_RTCIENR	(M328BASE+0xB10)	/* Interrupt Enable Reg */
#define	M328_RSTPWCH	(M328BASE+0xB12)	/* Stopwatch Minutes */
#endif
#endif