📄 twi.lst
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00E8 F011 BEQ 0x00EB
00E9 2700 CLR R16
00EA C027 RJMP 0x0112
(0124) Start();
00EB EA84 LDI R24,0xA4
00EC BF86 OUT 0x36,R24
(0125) Wait();
00ED B626 IN R2,0x36
00EE FE27 SBRS R2,7
00EF CFFD RJMP 0x00ED
(0126) if (TestAck()!=RE_START) return 0;
00F0 B181 IN R24,0x01
00F1 7F88 ANDI R24,0xF8
00F2 3180 CPI R24,0x10
00F3 F011 BEQ 0x00F6
00F4 2700 CLR R16
00F5 C01C RJMP 0x0112
(0127) Write8Bit(rd_device_add);
00F6 EA81 LDI R24,0xA1
00F7 B983 OUT 0x03,R24
00F8 E884 LDI R24,0x84
00F9 BF86 OUT 0x36,R24
(0128) Wait();
00FA B626 IN R2,0x36
00FB FE27 SBRS R2,7
00FC CFFD RJMP 0x00FA
(0129) if(TestAck()!=MR_SLA_ACK) return 0;
00FD B181 IN R24,0x01
00FE 7F88 ANDI R24,0xF8
00FF 3480 CPI R24,0x40
0100 F011 BEQ 0x0103
0101 2700 CLR R16
0102 C00F RJMP 0x0112
(0130) Twi();
0103 E884 LDI R24,0x84
0104 BF86 OUT 0x36,R24
(0131) Wait();
0105 B626 IN R2,0x36
0106 FE27 SBRS R2,7
0107 CFFD RJMP 0x0105
(0132) if(TestAck()!=MR_DATA_NOACK) return 0;
0108 B181 IN R24,0x01
0109 7F88 ANDI R24,0xF8
010A 3588 CPI R24,0x58
010B F011 BEQ 0x010E
010C 2700 CLR R16
010D C004 RJMP 0x0112
(0133) temp=TWDR;
010E B143 IN R20,0x03
(0134) Stop();
010F E984 LDI R24,0x94
0110 BF86 OUT 0x36,R24
(0135) return temp;
0111 2F04 MOV R16,R20
0112 940E01A3 CALL pop_gset1
0114 9508 RET
_i2c_Write:
Wdata --> R20
RomAddress --> R22
0115 940E019E CALL push_gset2
0117 2F42 MOV R20,R18
0118 2F60 MOV R22,R16
(0136) }
(0137)
(0138) /******************************************
(0139) I2C总线写一个字节
(0140) 返回0:写成功
(0141) 返回非0:写失败
(0142) *******************************************/
(0143) unsigned char i2c_Write(unsigned char RomAddress,unsigned char Wdata)
(0144) {
(0145) Start();
0119 EA84 LDI R24,0xA4
011A BF86 OUT 0x36,R24
(0146) Wait();
011B B626 IN R2,0x36
011C FE27 SBRS R2,7
011D CFFD RJMP 0x011B
(0147) if(TestAck()!=START) return 1;
011E B181 IN R24,0x01
011F 7F88 ANDI R24,0xF8
0120 3088 CPI R24,0x8
0121 F011 BEQ 0x0124
0122 E001 LDI R16,1
0123 C02B RJMP 0x014F
(0148) Write8Bit(wr_device_add);
0124 EA80 LDI R24,0xA0
0125 B983 OUT 0x03,R24
0126 E884 LDI R24,0x84
0127 BF86 OUT 0x36,R24
(0149) Wait();
0128 B626 IN R2,0x36
0129 FE27 SBRS R2,7
012A CFFD RJMP 0x0128
(0150) if(TestAck()!=MT_SLA_ACK) return 1;
012B B181 IN R24,0x01
012C 7F88 ANDI R24,0xF8
012D 3188 CPI R24,0x18
012E F011 BEQ 0x0131
012F E001 LDI R16,1
0130 C01E RJMP 0x014F
(0151) Write8Bit(RomAddress);
0131 B963 OUT 0x03,R22
0132 E884 LDI R24,0x84
0133 BF86 OUT 0x36,R24
(0152) Wait();
0134 B626 IN R2,0x36
0135 FE27 SBRS R2,7
0136 CFFD RJMP 0x0134
(0153) if(TestAck()!=MT_DATA_ACK) return 1;
0137 B181 IN R24,0x01
0138 7F88 ANDI R24,0xF8
0139 3288 CPI R24,0x28
013A F011 BEQ 0x013D
013B E001 LDI R16,1
013C C012 RJMP 0x014F
(0154) Write8Bit(Wdata);
013D B943 OUT 0x03,R20
013E E884 LDI R24,0x84
013F BF86 OUT 0x36,R24
(0155) Wait();
0140 B626 IN R2,0x36
0141 FE27 SBRS R2,7
0142 CFFD RJMP 0x0140
(0156) if(TestAck()!=MT_DATA_ACK) return 1;
0143 B181 IN R24,0x01
0144 7F88 ANDI R24,0xF8
0145 3288 CPI R24,0x28
0146 F011 BEQ 0x0149
0147 E001 LDI R16,1
0148 C006 RJMP 0x014F
(0157) Stop();
0149 E984 LDI R24,0x94
014A BF86 OUT 0x36,R24
(0158) delay_ms(10);
014B E00A LDI R16,0xA
014C E010 LDI R17,0
014D DF17 RCALL _delay_ms
(0159) return 0;
014E 2700 CLR R16
014F 940E0195 CALL pop_gset2
0151 9508 RET
(0160) }
(0161)
(0162)
(0163) void twi_init(void)
(0164) {
(0165) TWCR= 0X00; //disable twi
_twi_init:
0152 2422 CLR R2
0153 BE26 OUT 0x36,R2
(0166) TWBR= 0x12; //set bit rate
0154 E182 LDI R24,0x12
0155 B980 OUT 0x00,R24
(0167) TWSR= 0x01; //set prescale
0156 E081 LDI R24,1
0157 B981 OUT 0x01,R24
(0168) TWCR= 0x04; //enable twi
0158 E084 LDI R24,4
0159 BF86 OUT 0x36,R24
015A 9508 RET
(0169)
(0170)
(0171)
(0172) }
(0173) //******************************************
(0174) void main(void)
(0175) {
(0176) uchar key_val,wr_val=0,rd_val,i,j;
_main:
i --> Y+1
key_val --> Y+1
wr_val --> R20
j --> R20
rd_val --> R22
k --> R10
015B 2744 CLR R20
(0177) uint k;
(0178) port_init();
015C DF61 RCALL _port_init
(0179) CS_OFF();
015D 9AC3 SBI 0x18,3
(0180) delay_ms(10);
015E E00A LDI R16,0xA
015F E010 LDI R17,0
0160 DF04 RCALL _delay_ms
(0181) delay_ms(10);
0161 E00A LDI R16,0xA
0162 E010 LDI R17,0
0163 DF01 RCALL _delay_ms
0164 C016 RJMP 0x017B
(0182) //twi_init();
(0183) while(1)
(0184) {
(0185) rd_val=12;
0165 E06C LDI R22,0xC
(0186)
(0187) //for(i=1; i<255;i++)
(0188) //{
(0189) // i2c_Write(i,i);
(0190) // _delay_us(20);
(0191)
(0192) //adc_to_disbuffer1(16);
(0193)
(0194) //
(0195) //}
(0196) for( j=1; j<255;j++)
0166 E041 LDI R20,1
0167 C011 RJMP 0x0179
(0197) {
(0198) for( k=1; k<1025;k++)
0168 E081 LDI R24,1
0169 E090 LDI R25,0
016A 015C MOVW R10,R24
016B C007 RJMP 0x0173
(0199) {
(0200) rd_val=i2c_Read(j);
016C 2F04 MOV R16,R20
016D DF57 RCALL _i2c_Read
016E 2F60 MOV R22,R16
(0201) display(rd_val);
FILE: <library>
016F DF14 RCALL _display
0170 01C5 MOVW R24,R10
0171 9601 ADIW R24,1
0172 015C MOVW R10,R24
0173 01C5 MOVW R24,R10
0174 3081 CPI R24,1
0175 E0E4 LDI R30,4
0176 079E CPC R25,R30
0177 F3A0 BCS 0x016C
0178 9543 INC R20
0179 3F4F CPI R20,0xFF
017A F368 BCS 0x0168
017B CFE9 RJMP 0x0165
017C 9508 RET
mod8u:
017D 9468 BSET 6
017E C001 RJMP xdiv8u
div8u:
017F 94E8 BCLR 6
xdiv8u:
0180 932A ST R18,-Y
0181 92FA ST R15,-Y
0182 92EA ST R14,-Y
0183 24FF CLR R15
0184 24EE CLR R14
0185 E120 LDI R18,0x10
0186 0F00 LSL R16
0187 1CFF ROL R15
0188 1CEE ROL R14
0189 16E1 CP R14,R17
018A F010 BCS 0x018D
018B 1AE1 SUB R14,R17
018C 9503 INC R16
018D 952A DEC R18
018E F7B9 BNE 0x0186
018F F40E BRTC 0x0191
0190 2D0E MOV R16,R14
0191 90E9 LD R14,Y+
0192 90F9 LD R15,Y+
0193 9129 LD R18,Y+
0194 9508 RET
pop_gset2:
0195 E0E2 LDI R30,2
0196 940C01A4 JMP pop
push_gset5:
0198 92FA ST R15,-Y
0199 92EA ST R14,-Y
push_gset4:
019A 92DA ST R13,-Y
019B 92CA ST R12,-Y
push_gset3:
019C 92BA ST R11,-Y
019D 92AA ST R10,-Y
push_gset2:
019E 937A ST R23,-Y
019F 936A ST R22,-Y
push_gset1:
01A0 935A ST R21,-Y
01A1 934A ST R20,-Y
01A2 9508 RET
pop_gset1:
01A3 E0E1 LDI R30,1
pop:
01A4 9149 LD R20,Y+
01A5 9159 LD R21,Y+
01A6 FDE0 SBRC R30,0
01A7 9508 RET
01A8 9169 LD R22,Y+
01A9 9179 LD R23,Y+
01AA FDE1 SBRC R30,1
01AB 9508 RET
01AC 90A9 LD R10,Y+
01AD 90B9 LD R11,Y+
01AE FDE2 SBRC R30,2
01AF 9508 RET
01B0 90C9 LD R12,Y+
01B1 90D9 LD R13,Y+
01B2 FDE3 SBRC R30,3
01B3 9508 RET
01B4 90E9 LD R14,Y+
01B5 90F9 LD R15,Y+
01B6 9508 RET
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