i21555.c

intel 21555PCI桥片驱动代码

	/* check for valid disable value */
	if(disable < 0 || disable > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set upstream DAC prefetch disable bit */
	if(disable == 1)
		{
		chipControl0 |= I21555_CC0_US_DAC_PREFETCH_DIS;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_US_DAC_PREFETCH_DIS;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetRetryCounterDisable - Set the Retry Counter Disable bit
*
* This function writes to the retry counter disable bit in the chip control 0 register. If
* disable = 0, all 2^24 retry counters in both directions are enabled. When the 21555 attempts
* a posted write or delayed transaction and receives 2^24 target retries, the transaction is
* discarded. If disable = 1, all retry counters are disabled and there is no limit to the
* number of attempts the 21555 makes when initiating a posted write or delayed transaction.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetRetryCounterDisable(PCI_LOC *i21555_dev, int disable)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid disable value */
	if(disable < 0 || disable > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set retry counter disable bit */
	if(disable == 1)
		{
		chipControl0 |= I21555_CC0_RETRY_CNTR;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_RETRY_CNTR;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetPrimaryPostedWriteThresh - Set the Primary Posted Write Threshold bit
*
* This function writes to the primary posted write threshold bit in the chip control 1 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following threshold values control when the 21555 returns retry to posted writes:
*     0 - Posted write queue is full when less than a cache line is free to post data
*     1 - Posted write queue is full when less than half a cache line is free to post data
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetSecondaryPostedWriteThresh()
*/
void i21555_SetPrimaryPostedWriteThresh(PCI_LOC *i21555_dev, int thresh)
	{
	UINT16 chipControl1 = 0;
	int old_interface = 0;

	/* check for valid threshold value */
	if(thresh < 0 || thresh > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 1 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, &chipControl1);

	/* set primary posted write threshold bit */
	if(thresh == 1)
		{
		chipControl1 |= I21555_CC1_PRI_POST_WR_THRESH;
		}
	else
		{
		chipControl1 &= ~I21555_CC1_PRI_POST_WR_THRESH;
		}

	/* write new value to chip control 1 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, chipControl1);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetSecondaryPostedWriteThresh - Set the Secondary Posted Write Threshold bit
*
* This function writes to the secondary posted write threshold bit in the chip control 1 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following threshold values control when the 21555 returns retry to posted writes:
*     0 - Posted write queue is full when less than a cache line is free to post data
*     1 - Posted write queue is full when less than half a cache line is free to post data
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetPrimaryPostedWriteThresh()
*/
void i21555_SetSecondaryPostedWriteThresh(PCI_LOC *i21555_dev, int thresh)
	{
	UINT16 chipControl1 = 0;
	int old_interface = 0;

	/* check for valid threshold value */
	if(thresh < 0 || thresh > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 1 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, &chipControl1);

	/* set secondary posted write threshold bit */
	if(thresh == 1)
		{
		chipControl1 |= I21555_CC1_SEC_POST_WR_THRESH;
		}
	else
		{
		chipControl1 &= ~I21555_CC1_SEC_POST_WR_THRESH;
		}

	/* write new value to chip control 1 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, chipControl1);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetPrimaryDelayedReadThresh - Set the Primary Delayed Read Threshold bits
*
* This function writes to the primary delayed read threshold bits in the chip control 1 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following threshold values control when the 21555 initiates a memory read:
*     0 - At least 8 DWORDs free in read data queue for all memory read commands
*     1 - Illegal (behaves the same as 0)
*     2 - At least one cache line free for MRL and MRM, 8 DWORDs free for memory read
*     3 - At least one cache line free for all memory read commands
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetSecondaryDelayedReadThresh()
*/
void i21555_SetPrimaryDelayedReadThresh(PCI_LOC *i21555_dev, int thresh)
	{
	UINT16 chipControl1 = 0;
	int old_interface = 0;

	/* check for valid threshold value */
	if(thresh < 0 || thresh > 3 || thresh == 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 1 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, &chipControl1);

	/* set primary delayed read threshold bits */
	chipControl1 &= 0xFFF3;
	chipControl1 |= (thresh & 3) << 2;

	/* write new value to chip control 1 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, chipControl1);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetSecondaryDelayedReadThresh - Set the Secondary Delayed Read Threshold bits
*
* This function writes to the secondary delayed read threshold bits in the chip control 1 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following threshold values control when the 21555 initiates a memory read:
*     0 - At least 8 DWORDs free in read data queue for all memory read commands
*     1 - Illegal (behaves the same as 0)
*     2 - At least one cache line free for MRL and MRM, 8 DWORDs free for memory read
*     3 - At least one cache line free for all memory read commands
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetPrimaryDelayedReadThresh()
*/
void i21555_SetSecondaryDelayedReadThresh(PCI_LOC *i21555_dev, int thresh)
	{
	UINT16 chipControl1 = 0;
	int old_interface = 0;

	/* check for valid threshold value */
	if(thresh < 0 || thresh > 3 || thresh == 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 1 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, &chipControl1);

	/* set secondary delayed read threshold bits */
	chipControl1 &= 0xFFCF;
	chipControl1 |= (thresh & 3) << 4;

	/* write new value to chip control 1 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_1, chipControl1);

	if(old_interface) setCurrentPciInterface(old_interface);
	}



/**********************************************************************************************
*
* i21555_SromReadByte - Read a Byte from the Serial Preload SROM
*
* This function reads one byte of data from the local 21555's 512 byte serial preload SROM.
*
*
* RETURNS: The data read from the SROM at addr.
*
* SEE ALSO: i21555_SromWriteByte()
*/
UINT8 i21555_SromReadByte(UINT16 addr)
	{
	UINT32 csrReg = 0;
	int old_interface = 0;
	UINT8 data = 0xff;
	PCI_LOC *i21555_dev = &i21555_localDev;

	old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);

	/* get address of CSR registers */
	pciConfigInLong(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CSR_IO_BAR, &csrReg);
	csrReg &= PCI_IOBASE_MASK;

	if(csrReg)
		{

		/* Verify that both parallel and serial busy bits are clear */
		if(PCI_IN_BYTE(csrReg + I21555_CSR_ROM_CONTROL) & (BIT0 | BIT1))
			{
			if(old_interface) setCurrentPciInterface(old_interface);
			return data;
			}

		/* Set Address and Opcode */
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_ADDR, addr & 0xff);
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_ADDR + 1, 4 | ((addr >> 8) & 1));

		/* Set Start bit */
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_CONTROL, BIT0);

		/* Wait for the read to complete */
		while(PCI_IN_BYTE(csrReg + I21555_CSR_ROM_CONTROL) & BIT0) {}

		data = PCI_IN_BYTE(csrReg + I21555_CSR_ROM_DATA);
		}

	if(old_interface) setCurrentPciInterface(old_interface);
	return data;
	}


/**********************************************************************************************
*
* i21555_SromWriteByte - Write a Byte to the Serial Preload SROM
*
* This function writes one byte of data to the local 21555's 512 byte serial preload SROM.
*
*
* RETURNS: 0 if successful or -1 if not successful.
*
* SEE ALSO: i21555_SromWriteEnable(), i21555_SromWriteDisable(), i21555_SromReadByte()
*/
int i21555_SromWriteByte(UINT16 addr, UINT8 data)
	{
	UINT32 csrReg = 0;
	int old_interface = 0;
	PCI_LOC *i21555_dev = &i21555_localDev;

	old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);

	/* get address of CSR registers */
	pciConfigInLong(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CSR_IO_BAR, &csrReg);
	csrReg &= PCI_IOBASE_MASK;

	if(csrReg)
		{

		/* Verify that both parallel and serial busy bits are clear */
		if(PCI_IN_BYTE(csrReg + I21555_CSR_ROM_CONTROL) & (BIT0 | BIT1))
			{
			if(old_interface) setCurrentPciInterface(old_interface);
			return -1;
			}

		/* Set Address and Opcode */
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_ADDR, addr & 0xff);
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_ADDR + 1, 2 | ((addr >> 8) & 1));

		/* Set the data */
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_DATA, data);

		/* Set Start bit */
		PCI_OUT_BYTE(csrReg + I21555_CSR_ROM_CONTROL, BIT0);

		/* Wait for the write command to complete */
		while(PCI_IN_BYTE(csrReg + I21555_CSR_ROM_CONTROL) & BIT0) {}

		/* Poll until the write is complete */
		while(PCI_IN_BYTE(csrReg + I21555_CSR_ROM_CONTROL) & BIT3)
			{
			PCI_OUT_BYTE(csrReg + I21555_CSR_