i21555.c

intel 21555PCI桥片驱动代码

* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_WriteUpstreamMem1Setup(PCI_LOC *i21555_dev, int enable, UINT32 size, int prefetch, int below_1MB)
	{
	UINT32 setupReg = 0;

	/* i21555 device must be given, local 21555 register is not writable */
	if(i21555_dev == NULL) return;

	/* set size */
	setupReg = (~(size - 1)) & 0x7FFFF000;

	/* set enable bit */
	if(enable) setupReg |= BIT31;

	/* set prefetchable bit */
	if(prefetch) setupReg |= BIT3;

	/* set bit that indicates the address must be below 1 MB */
	if(below_1MB) setupReg |= BIT1;

	/* write the setup register */
	pciConfigOutLong(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_US_MEM1_SETUP, setupReg);
	}


/**********************************************************************************************
*
* i21555_SetMasterAbortMode - Set the Master Abort Mode
*
* This function writes to the master abort mode bit in the chip control 0 register. This bit
* controls the 21555's behavior on the initiator bus when a master abort termination occurs
* in response to a delayed transaction initiated by the 21555 on the target bus.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following are valid mode values:
*     0 - The 21555 asserts TRDY# and returns FFFFFFFF if a read. SERR is not asserted.
*     1 - The 21555 returns a target abort. SERR is asserted if enabled.
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetMasterAbortMode(PCI_LOC *i21555_dev, int mode)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid mode value */
	if(mode < 0 || mode > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set master abort mode bit */
	if(mode == 1)
		{
		chipControl0 |= I21555_CC0_MASTER_ABORT_MODE;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_MASTER_ABORT_MODE;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetMemWriteDisconnectControl - Set the Memory Write Disconnect Control bit
*
* This function writes to the memory write disconnect control bit in the chip control 0 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following modes control the disconnect boundary for memory writes (except MWI):
*     0 - Disconnect on 4KB boundary, page boundary < 4KB or when posted write queue is full.
*     1 - Disconnect on cache line boundary or when the posted write queue is full.
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetMemWriteDisconnectControl(PCI_LOC *i21555_dev, int mode)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid mode value */
	if(mode < 0 || mode > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set memory write disconnect control bit */
	if(mode == 1)
		{
		chipControl0 |= I21555_CC0_MEM_WR_DISCONN_CTL;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_MEM_WR_DISCONN_CTL;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetPrimaryMasterTimeout - Set the Primary Master Timeout value
*
* This function writes to the primary master timeout bits in the chip control 0 register. The
* master timeout value controls how many PCI clock cycles the 21555 will wait for an initiator
* to repeat a delayed transaction request. If the initiator has not repeated the transaction at
* least once before the counter expires, the 21555 discards the transaction from its queues.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following timeout values are allowed:
*     0 - Disable the timeout counter. The 21555 will wait indefinately.
*     1 - Wait 2^10 PCI clocks
*     2 - Wait 2^15 PCI clocks 
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetSecondaryMasterTimeout()
*/
void i21555_SetPrimaryMasterTimeout(PCI_LOC *i21555_dev, int timeout)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid timeout value */
	if(timeout < 0 || timeout > 2) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set master timeout bits */
	switch(timeout)
		{
		case 0: /* disabled */
			chipControl0 |= I21555_CC0_PRI_MSTR_TOUT_DIS;
			break;

		case 1: /* 2^10 PCI clocks */
			chipControl0 &= ~I21555_CC0_PRI_MSTR_TOUT_DIS;
			chipControl0 |= I21555_CC0_PRI_MSTR_TOUT;
			break;

		case 2: /* 2^15 PCI clocks */
			chipControl0 &= ~I21555_CC0_PRI_MSTR_TOUT_DIS;
			chipControl0 &= ~I21555_CC0_PRI_MSTR_TOUT;
			break;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetSecondaryMasterTimeout - Set the Secondary Master Timeout value
*
* This function writes to the secondary master timeout bits in the chip control 0 register. The
* master timeout value controls how many PCI clock cycles the 21555 will wait for an initiator
* to repeat a delayed transaction request. If the initiator has not repeated the transaction at
* least once before the counter expires, the 21555 discards the transaction from its queues.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following timeout values are allowed:
*     0 - Disable the timeout counter. The 21555 will wait indefinately.
*     1 - Wait 2^10 PCI clocks
*     2 - Wait 2^15 PCI clocks 
*
*
* RETURNS: NA.
*
* SEE ALSO: i21555_SetPrimaryMasterTimeout()
*/
void i21555_SetSecondaryMasterTimeout(PCI_LOC *i21555_dev, int timeout)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid timeout value */
	if(timeout < 0 || timeout > 2) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set master timeout bits */
	switch(timeout)
		{
		case 0: /* disabled */
			chipControl0 |= I21555_CC0_SEC_MSTR_TOUT_DIS;
			break;

		case 1: /* 2^10 PCI clocks */
			chipControl0 &= ~I21555_CC0_SEC_MSTR_TOUT_DIS;
			chipControl0 |= I21555_CC0_SEC_MSTR_TOUT;
			break;

		case 2: /* 2^15 PCI clocks */
			chipControl0 &= ~I21555_CC0_SEC_MSTR_TOUT_DIS;
			chipControl0 &= ~I21555_CC0_SEC_MSTR_TOUT;
			break;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetDelayedTransOrderControl - Set the Delayed Transaction Order Control bit
*
* This function writes to the delayed transaction order control bit in the chip control 0 register.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
* The following modes control how the 21555 initiates delayed transactions on the target bus:
*     0 - After receiving a target retry, the 21555 can initiate a different queued transaction
*     1 - The 21555 attempts the same transaction until a response other than target retry is received
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetDelayedTransOrderControl(PCI_LOC *i21555_dev, int mode)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid mode value */
	if(mode < 0 || mode > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set delayed transaction order control bit */
	if(mode == 1)
		{
		chipControl0 |= I21555_CC0_DLYD_TRANS_ORDER_CTL;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_DLYD_TRANS_ORDER_CTL;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetSERRForwardEnable - Set the SERR# Forward Enable bit
*
* This function writes to the SERR# forward enable bit in the chip control 0 register. If
* enable = 0, the 21555 does not assert p_serr_l as a result of s_serr_l assertion. If enable = 1,
* the 21555 asserts p_serr_l when s_serr_l is asserted and the primary SERR# enable bit is set.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetSERRForwardEnable(PCI_LOC *i21555_dev, int enable)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;

	/* check for valid enable value */
	if(enable < 0 || enable > 1) return;

	/* if 21555 device not specified, use local device */
	if(i21555_dev == NULL)
		{
		i21555_dev = &i21555_localDev;
		old_interface = setCurrentPciInterface(PCI_LOCAL_INTERFACE);
		}

	/* read current chip control 0 value */
	pciConfigInWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, &chipControl0);

	/* set SERR# forward enable bit */
	if(enable == 1)
		{
		chipControl0 |= I21555_CC0_SERR_FORWARD_EN;
		}
	else
		{
		chipControl0 &= ~I21555_CC0_SERR_FORWARD_EN;
		}

	/* write new value to chip control 0 */
	pciConfigOutWord(i21555_dev->bus, i21555_dev->device, i21555_dev->function,
		I21555_CONFIG_CHIP_CONTROL_0, chipControl0);

	if(old_interface) setCurrentPciInterface(old_interface);
	}


/**********************************************************************************************
*
* i21555_SetUpstreamDACPrefetchDisable - Set the Upstream Dual Address Cycle Prefetch Disable bit
*
* This function writes to the upstream DAC prefetch disable bit in the chip control 0 register.
* If disable = 0, prefetching is performed for upstream  dual address cycle (DAC) memory reads.
* If disable = 1, upstream DACs using the memory read bus command are not prefetched. Transactions
* are limited to a single DWORD and byte enables are preserved.
* This function may operate on the local (on-board) 21555 or an off-board 21555. When operating
* on the local 21555 set i21555_dev = NULL. Otherwise, i21555_dev must point to the bus, device,
* and function of the 21555 to operate on.
*
*
* RETURNS: NA.
*
* SEE ALSO: 
*/
void i21555_SetUpstreamDACPrefetchDisable(PCI_LOC *i21555_dev, int disable)
	{
	UINT16 chipControl0 = 0;
	int old_interface = 0;