gtpci.h

intel 21555PCI桥片驱动代码

/*******************************************************************************
*                   Copyright 2002, GALILEO TECHNOLOGY, LTD.                   *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL.                      *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
*                                                                              *
* MARVELL COMPRISES MARVELL TECHNOLOGY GROUP LTD. (MTGL) AND ITS SUBSIDIARIES, *
* MARVELL INTERNATIONAL LTD. (MIL), MARVELL TECHNOLOGY, INC. (MTI), MARVELL    *
* SEMICONDUCTOR, INC. (MSI), MARVELL ASIA PTE LTD. (MAPL), MARVELL JAPAN K.K.  *
* (MJKK), GALILEO TECHNOLOGY LTD. (GTL) AND GALILEO TECHNOLOGY, INC. (GTI).    *
********************************************************************************
* gtPci.h - PCI functions header file.
*
* DESCRIPTION:
*       None.
*
* DEPENDENCIES:
*       None.
*
*******************************************************************************/

#ifndef __INCgtPcih
#define __INCgtPcih

/* includes */
#include "gtCore.h"

#ifdef __cplusplus
extern "C" {
#endif

/* defines */
#define PCI_MAX_DEVICES                     32
#define PCI_SELF                            32

/* 4KB granularity */
#define MINIMUM_WINDOW_SIZE                 0x1000
#define MINIMUM_BAR_SIZE                    0x1000

/* PCI base address low bar mask */
#define BAR_MASK                            0xfffff000

#define PCI_ERROR_CODE                      0xffffffff

#define PCI_VENDOR_ID_MASK                  0x0000ffff

#define PCI_BUS_NUMBER_MASK                 0x00ff0000
#define PCI_DEV_NUMBER_MASK                 0x0000f800
#define PCI_FUNCTION_NUMBER_MASK            0x00000700
#define PCI_REG_OFFSET_MASK                 0x000000fc


#define PCI_MASTER_ENABLE		                   BIT2
#define	PCI_MEMORY_ENABLE		                   BIT1
#define	PCI_I_O_ENABLE  		                   BIT0

/* Definitions for code clarification, not to be used specifically. */
#define PCI_MASTER_ABORT                           BIT8
#define PCI_CONFIG_ENABLE                          BIT31
#define PCI_TYPE0                                  NO_BIT
#define PCI_TYPE1                                  BIT0
#define PCI_OPERATION_MODE                         (BIT4|BIT5)

/************************************************************/
/* Definition for the access regions (from the slave side). */
/************************************************************/

/* Enables the access control mechanism */
#define PCI_ACCESS_CONTROL_WINDOW_ENABLE           BIT0
/* PCI master always asserts REQ64*. This feature is Only relevant if
   the target is the peer PCI interface (P2P gtMemory transaction) */
#define PCI_REQ64_ENABLE                           BIT1

#ifdef INCLUDE_SNOOP_SUPPORT
    /* Cache Coherency support.
       NOTE: Only relevant if the target is SDRAM .
             In PCIX mode - if bit[30] in the attribute phase
             (no Snoop) is asserted, these bit are ignored. */
    #define PCI_NON_COHERENT_REGION                NO_BIT
    #define PCI_CACHE_COHERENT_WT_REGION           BIT2
    #define PCI_CACHE_COHERENT_WB_REGION           BIT3
#endif /* INCLUDE_SNOOP_SUPPORT */

/*   Access Protect  */
#define PCI_ACCESS_FORBBIDEN                       BIT4

/*   Write Protect   */
#define PCI_WRITE_FORBBIDEN                        BIT5

/*   PCI slave Data Swap Control   */
#define PCI_NO_SWAP                                BIT6
#define PCI_BYTE_AND_WORD_SWAP                     BIT7
#define PCI_WORD_SWAP                              (BIT7|BIT6)
/*   Max burst control.
    Specifies the maximum burst size for a single transac-
    tion between a PCI slave and the other interfaces
    NOTE: In case of cache coherent region(bit[3:2] are
          0x1 or 0x2), the maximum burst is 32 bytes
          regardless of MBurst setting */
#define PCI_MAX_BURST_32                           NO_BIT
#define PCI_MAX_BURST_64                           BIT8
#define PCI_MAX_BURST_128                          BIT9
/*  Typical PCI read transaction Size. Defines the amount
    of data the slave prefetch from the target unit.
    Only relevant to conventional PCI mode.  */
#define PCI_READ_TRANSACTION_SIZE_32_BYTES         NO_BIT
#define PCI_READ_TRANSACTION_SIZE_64_BYTES         BIT10
#define PCI_READ_TRANSACTION_SIZE_128_BYTES        BIT11
#define PCI_READ_TRANSACTION_SIZE_256_BYTES        (BIT10|BIT11)

/* Macros */

/* The following macros set (or reset) a PCI agent (including PCI_SELF) to
   become either a master or slave. Additional macros set only the IO or memory
   enable bit, which are both set if the slave enable macro is used. */

#define GT_PCI_0_MASTER_ENABLE(deviceNumber) gtPci0WriteConfigReg(             \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MASTER_ENABLE |              \
          gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_0_MASTER_DISABLE(deviceNumber) gtPci0WriteConfigReg(            \
          PCI_STATUS_AND_COMMAND,deviceNumber,~PCI_MASTER_ENABLE &             \
          gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_0_MEMORY_ENABLE(deviceNumber) gtPci0WriteConfigReg(             \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MEMORY_ENABLE |              \
          gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_0_IO_ENABLE(deviceNumber) gtPci0WriteConfigReg(                 \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_I_O_ENABLE |                 \
          gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_0_SLAVE_ENABLE(deviceNumber) gtPci0WriteConfigReg(              \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MEMORY_ENABLE |              \
          PCI_I_O_ENABLE | gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,         \
                                                     deviceNumber))

#define GT_PCI_0_DISABLE(deviceNumber) gtPci0WriteConfigReg(                   \
          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                    \
          gtPci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#ifdef INCLUDE_PCI_1
#define GT_PCI_1_MASTER_ENABLE(deviceNumber) gtPci1WriteConfigReg(             \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MASTER_ENABLE |              \
          gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_1_MASTER_DISABLE(deviceNumber) gtPci1WriteConfigReg(            \
          PCI_STATUS_AND_COMMAND,deviceNumber,~PCI_MASTER_ENABLE &             \
          gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_1_MEMORY_ENABLE(deviceNumber) gtPci1WriteConfigReg(             \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MEMORY_ENABLE |              \
          gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_1_IO_ENABLE(deviceNumber) gtPci1WriteConfigReg(                 \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_I_O_ENABLE |                 \
          gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#define GT_PCI_1_SLAVE_ENABLE(deviceNumber) gtPci1WriteConfigReg(              \
          PCI_STATUS_AND_COMMAND,deviceNumber,PCI_MEMORY_ENABLE |              \
          PCI_I_O_ENABLE | gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,         \
                                                     deviceNumber))

#define GT_PCI_1_DISABLE(deviceNumber) gtPci1WriteConfigReg(                   \
          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                    \
          gtPci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))

#endif /* INCLUDE_PCI_1 */


/* typedefs */

typedef enum _pciInternalBAR{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
                             PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
                             PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
                             PCI_MEM_MAPPED_INTERNAL_REG_BAR,
                             PCI_IO_MAPPED_INTERNAL_REG_BAR

/* These values are not valid if the MV device does not support the features. */
#ifdef INCLUDE_P2P
                             ,PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR, PCI_P2P_IO_BAR
#endif

#ifdef INCLUDE_CPU_MAPPING 
                             ,PCI_CPU_BAR
#endif
                             ,PCI_INTERNAL_SRAM_BAR
                            } PCI_INTERNAL_BAR;

typedef enum _pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5
                              } PCI_ACCESS_REGIONS;

typedef enum _pciBusMode      {CONVENTIONAL_PCI,PCI_X_66MHZ,PCI_X_100MHZ,
                               PCI_X_133MHZ
                              } PCI_BUS_MODE;

typedef enum _pciAgentPark    {PARK_ON_AGENT, DONT_PARK_ON_AGENT
                              } PCI_AGENT_PARK;

typedef enum _pciBusFreq      {PCI_33MHZ, PCI_66MHZ
                              } PCI_BUS_FREQ;

typedef enum _pciBarMapping   {PCI_MEMORY_BAR, PCI_IO_BAR, PCI_NO_MAPPING
                              } PCI_BAR_MAPPING;

typedef enum _pciBarType      {PCI_32BIT_BAR = 0x0, PCI_RESERVED = 0x01,
                               PCI_64BIT_BAR = 0x2
                              } PCI_BAR_TYPE;