📄 i21555.h
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#include "vxWorks.h"
#include "config.h"
#include "cpc7510.h"
#include "pciAutoConfigLib.h"
/* 21555 BAR Registers that are manually set when the CPC7510 is the CPCI system controller */
#define I21555_CSRMEM_ADDRESS (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE - _4K)
#define I21555_CSRIO_ADDRESS (PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE - 0x100)
/* This is the offset used to access the standard *
* pci config registers for the opposite interface. *
* For example, to access the secondary interface *
* command register from the primary interface, use *
* the standard offset (0x04) plus the thru bridge *
* offset (0x40) = 0x44. */
#define I21555_CONFIG_THRU_BRIDGE_OFFSET 0x40
/* Intel 21555 Configuration Register Offsets */
#define I21555_CONFIG_CSR_MEM_BAR 0x10
#define I21555_CONFIG_CSR_IO_BAR 0x14
#define I21555_CONFIG_DS_IO_MEM1_BAR 0x18
#define I21555_CONFIG_DS_MEM2_BAR 0x1C
#define I21555_CONFIG_DS_MEM3_BAR_LO 0x20
#define I21555_CONFIG_DS_MEM3_BAR_HI 0x24
#define I21555_CONFIG_US_IO_MEM0_BAR 0x18
#define I21555_CONFIG_US_MEM1_BAR 0x1C
#define I21555_CONFIG_US_MEM2_BAR 0x20
#define I21555_CONFIG_DS_CONFIG_ADDR 0x80
#define I21555_CONFIG_DS_CONFIG_DATA 0x84
#define I21555_CONFIG_US_CONFIG_ADDR 0x88
#define I21555_CONFIG_US_CONFIG_DATA 0x8C
#define I21555_CONFIG_DS_CONFIG_OWN 0x90
#define I21555_CONFIG_US_CONFIG_OWN 0x91
#define I21555_CONFIG_CONFIG_CSR 0x92
#define I21555_CONFIG_DS_MEM0_XLAT_BASE 0x94
#define I21555_CONFIG_DS_IO_MEM1_XLAT_BASE 0x98
#define I21555_CONFIG_DS_MEM2_XLAT_BASE 0x9C
#define I21555_CONFIG_DS_MEM3_XLAT_BASE 0xA0
#define I21555_CONFIG_US_IO_MEM0_XLAT_BASE 0xA4
#define I21555_CONFIG_US_MEM1_XLAT_BASE 0xA8
#define I21555_CONFIG_DS_MEM0_SETUP 0xAC
#define I21555_CONFIG_DS_IO_MEM1_SETUP 0xB0
#define I21555_CONFIG_DS_MEM2_SETUP 0xB4
#define I21555_CONFIG_DS_MEM3_SETUP_LO 0xB8
#define I21555_CONFIG_DS_MEM3_SETUP_HI 0xBC
#define I21555_CONFIG_EXP_ROM_SETUP 0xC0
#define I21555_CONFIG_US_IO_MEM0_SETUP 0xC4
#define I21555_CONFIG_US_MEM1_SETUP 0xC8
#define I21555_CONFIG_CHIP_CONTROL_0 0xCC
#define I21555_CC0_MASTER_ABORT_MODE BIT0
#define I21555_CC0_MEM_WR_DISCONN_CTL BIT1
#define I21555_CC0_PRI_MSTR_TOUT BIT2
#define I21555_CC0_SEC_MSTR_TOUT BIT3
#define I21555_CC0_PRI_MSTR_TOUT_DIS BIT4
#define I21555_CC0_SEC_MSTR_TOUT_DIS BIT5
#define I21555_CC0_DLYD_TRANS_ORDER_CTL BIT6
#define I21555_CC0_SERR_FORWARD_EN BIT7
#define I21555_CC0_US_DAC_PREFETCH_DIS BIT8
#define I21555_CC0_MULT_DEV_EN BIT9
#define I21555_CC0_PRI_LOCKOUT BIT10
#define I21555_CC0_SEC_CLK_DIS BIT11
#define I21555_CC0_LUT_PG_EXT BIT12
#define I21555_CC0_RETRY_CNTR BIT13
#define I21555_CONFIG_CHIP_CONTROL_1 0xCE
#define I21555_CC1_PRI_POST_WR_THRESH BIT0
#define I21555_CC1_SEC_POST_WR_THRESH BIT1
#define I21555_CC1_I2O_EN BIT12
#define I21555_CONFIG_CHIP_STATUS 0xD0
#define I21555_CONFIG_ARB_CONTROL 0xD2
#define I21555_CONFIG_PRI_SERR_DISABLE 0xD4
#define I21555_CONFIG_SEC_SERR_DISABLE 0xD5
#define I21555_CONFIG_MODE_SET_CONFIG 0xD6
#define I21555_CONFIG_RESET_CONTROL 0xD8
#define I21555_CONFIG_PM_CAP_ID 0xDC
#define I21555_CONFIG_PM_NEXT_PTR 0xDD
#define I21555_CONFIG_PM_CAP 0xDE
#define I21555_CONFIG_PM_CSR 0xE0
#define I21555_CONFIG_PMCSR_BRIDGE_SUP_EXT 0xE2
#define I21555_CONFIG_PM_DATA 0xE3
#define I21555_CONFIG_VPD_CAP_ID 0xE4
#define I21555_CONFIG_VPD_NEXT_PTR 0xE5
#define I21555_CONFIG_VPD_ADDR 0xE6
#define I21555_CONFIG_VPD_DATA 0xE8
#define I21555_CONFIG_HS_CAP_ID 0xEC
#define I21555_CONFIG_HS_NEXT_PTR 0xED
#define I21555_CONFIG_HS_CONTROL 0xEE
/* Intel 21555 CSR register Offsets */
#define I21555_CSR_DS_CONFIG_ADDR 0x0000
#define I21555_CSR_DS_CONFIG_DATA 0x0004
#define I21555_CSR_US_CONFIG_ADDR 0x0008
#define I21555_CSR_US_CONFIG_DATA 0x000C
#define I21555_CSR_DS_CONFIG_OWN 0x0010
#define I21555_CSR_US_CONFIG_OWN 0x0011
#define I21555_CSR_CONFIG_CSR 0x0012
#define I21555_CSR_DS_IO_ADDR 0x0014
#define I21555_CSR_DS_IO_DATA 0x0018
#define I21555_CSR_US_IO_ADDR 0x001C
#define I21555_CSR_US_IO_DATA 0x0020
#define I21555_CSR_DS_IO_OWN 0x0024
#define I21555_CSR_US_IO_OWN 0x0025
#define I21555_CSR_IO_OWN_CSR 0x0026
#define I21555_CSR_LUT_OFFSET 0x0028
#define I21555_CSR_LUT_DATA 0x002C
#define I21555_CSR_DS_MEM0_XLAT_BASE 0x0068
#define I21555_CSR_DS_IO_MEM1_XLAT_BASE 0x006C
#define I21555_CSR_DS_MEM2_XLAT_BASE 0x0070
#define I21555_CSR_DS_MEM3_XLAT_BASE 0x0074
#define I21555_CSR_US_IO_MEM0_XLAT_BASE 0x0078
#define I21555_CSR_US_MEM1_XLAT_BASE 0x007C
#define I21555_CSR_CHIP_STATUS_CSR 0x0082
#define I21555_CSR_SET_IRQ_MASK 0x0084
#define I21555_CSR_CLEAR_IRQ_MASK 0x0086
#define I21555_CSR_US_PG_BOUND_IRQ0 0x0088
#define I21555_CSR_US_PG_BOUND_IRQ1 0x008C
#define I21555_CSR_US_PG_BOUND_IRQ0_MASK 0x0090
#define I21555_CSR_US_PG_BOUND_IRQ1_MASK 0x0094
#define I21555_CSR_PRI_CLEAR_IRQ 0x0098
#define I21555_CSR_SEC_CLEAR_IRQ 0x009A
#define I21555_CSR_PRI_SET_IRQ 0x009C
#define I21555_CSR_SEC_SET_IRQ 0x009E
#define I21555_CSR_PRI_CLEAR_IRQ_MASK 0x00A0
#define I21555_CSR_SEC_CLEAR_IRQ_MASK 0x00A2
#define I21555_CSR_PRI_SET_IRQ_MASK 0x00A4
#define I21555_CSR_SEC_SET_IRQ_MASK 0x00A6
#define I21555_CSR_SCRATCH0 0x00A8
#define I21555_CSR_SCRATCH1 0x00AC
#define I21555_CSR_SCRATCH2 0x00B0
#define I21555_CSR_SCRATCH3 0x00B4
#define I21555_CSR_SCRATCH4 0x00B8
#define I21555_CSR_SCRATCH5 0x00BC
#define I21555_CSR_SCRATCH6 0x00C0
#define I21555_CSR_SCRATCH7 0x00C4
#define I21555_CSR_ROM_SETUP 0x00C8
#define I21555_CSR_ROM_DATA 0x00CA
#define I21555_CSR_ROM_ADDR 0x00CC
#define I21555_CSR_ROM_CONTROL 0x00CF
#define I21555_CSR_GENERIC_OWN 0x00D0
#define I21555_CSR_US_MEM2_LUT 0x0100
/* Downstream configuration access */
void i21555_DownstreamConfigEnable(void);
UINT32 i21555_DownstreamReadConfigLong(PCI_LOC *downstream_dev, UINT32 regOffset);
void i21555_DownstreamWriteConfigLong(PCI_LOC *downstream_dev, UINT32 regOffset, UINT32 data);
void i21555_DownstreamWriteConfigWord(PCI_LOC *downstream_dev, UINT32 regOffset, UINT16 data);
void i21555_DownstreamWriteConfigByte(PCI_LOC *downstream_dev, UINT32 regOffset, UINT8 data);
/* Downstream configuration access through a PCI-PCI Bridge */
UINT32 i21555_DownstreamOverBridgeReadConfigLong(PCI_LOC *downstream_dev, UINT32 regOffset);
void i21555_DownstreamOverBridgeWriteConfigLong(PCI_LOC *downstream_dev, UINT32 regOffset, UINT32 data);
void i21555_DownstreamOverBridgeWriteConfigWord(PCI_LOC *downstream_dev, UINT32 regOffset, UINT16 data);
void i21555_DownstreamOverBridgeWriteConfigByte(PCI_LOC *downstream_dev, UINT32 regOffset, UINT8 data);
/* Doorbell interrupts */
UINT16 i21555_PrimaryDoorbellIrqStatus(PCI_LOC *i21555_dev);
void i21555_PrimaryDoorbellIrqSet(PCI_LOC *i21555_dev, int irq_bit);
void i21555_PrimaryDoorbellIrqClear(PCI_LOC *i21555_dev, int irq_bit);
void i21555_PrimaryDoorbellIrqMask(PCI_LOC *i21555_dev, int irq_bit);
void i21555_PrimaryDoorbellIrqUnmask(PCI_LOC *i21555_dev, int irq_bit);
UINT16 i21555_SecondaryDoorbellIrqStatus(PCI_LOC *i21555_dev);
void i21555_SecondaryDoorbellIrqSet(PCI_LOC *i21555_dev, int irq_bit);
void i21555_SecondaryDoorbellIrqClear(PCI_LOC *i21555_dev, int irq_bit);
void i21555_SecondaryDoorbellIrqMask(PCI_LOC *i21555_dev, int irq_bit);
void i21555_SecondaryDoorbellIrqUnmask(PCI_LOC *i21555_dev, int irq_bit);
/* Scratchpad Registers */
UINT32 i21555_ReadScratchpadReg(PCI_LOC *i21555_dev, int reg);
void i21555_WriteScratchpadReg(PCI_LOC *i21555_dev, int reg, UINT32 data);
/* Downstream/Upstream BAR Setup Registers */
void i21555_WriteDownstreamMem0Setup(PCI_LOC *i21555_dev, UINT32 size, int prefetch, int below_1MB);
void i21555_WriteDownstreamIoMem1Setup(PCI_LOC *i21555_dev, int enable, UINT32 size, int prefetch,
int below_1MB, int io);
void i21555_WriteDownstreamMem2Setup(PCI_LOC *i21555_dev, int enable, UINT32 size, int prefetch,
int below_1MB);
void i21555_WriteDownstreamMem3Setup(PCI_LOC *i21555_dev, int enable, UINT32 size_hi, UINT32 size_lo,
int prefetch, int type);
void i21555_WriteUpstreamIoMem0Setup(PCI_LOC *i21555_dev, int enable, UINT32 size, int prefetch,
int below_1MB, int io);
void i21555_WriteUpstreamMem1Setup(PCI_LOC *i21555_dev, int enable, UINT32 size, int prefetch,
int below_1MB);
/* Chip Control Settings */
void i21555_SetMasterAbortMode(PCI_LOC *i21555_dev, int mode);
void i21555_SetMemWriteDisconnectControl(PCI_LOC *i21555_dev, int mode);
void i21555_SetPrimaryMasterTimeout(PCI_LOC *i21555_dev, int timeout);
void i21555_SetSecondaryMasterTimeout(PCI_LOC *i21555_dev, int timeout);
void i21555_SetDelayedTransOrderControl(PCI_LOC *i21555_dev, int mode);
void i21555_SetSERRForwardEnable(PCI_LOC *i21555_dev, int enable);
void i21555_SetUpstreamDACPrefetchDisable(PCI_LOC *i21555_dev, int disable);
void i21555_SetRetryCounterDisable(PCI_LOC *i21555_dev, int disable);
void i21555_SetPrimaryPostedWriteThresh(PCI_LOC *i21555_dev, int thresh);
void i21555_SetSecondaryPostedWriteThresh(PCI_LOC *i21555_dev, int thresh);
void i21555_SetPrimaryDelayedReadThresh(PCI_LOC *i21555_dev, int thresh);
void i21555_SetSecondaryDelayedReadThresh(PCI_LOC *i21555_dev, int thresh);
/* Serial Preload SROM */
UINT8 i21555_SromReadByte(UINT16 addr);
int i21555_SromWriteByte(UINT16 addr, UINT8 data);
void i21555_SromWriteEnable();
void i21555_SromWriteDisable();
/* Manual setup of Intel 21555 PCI - PCI Bridge for CPCI access */
void i21555_cpci_init(void);
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