2410iis.c

S3C2410 USB Mass storage 源码.

//====================================================================
// File Name : 2410iis.c
// Function  : S3C2410 IIS (UDA1341) Record & Play Test Program
//             (DMA2, Double Buffer, Record, Play)
// Program   : Shin, On Pil (SOP)
// Date      : October 01, 2002
// Version   : 0.0
// History
//   0.0 : Programming start (March 06, 2002) -> SOP
//   0.1 : Added Slave mode Test Program(July 24, 2002) -> KWT(Tark), SOP
//         Optimization (December 09, 2002) -> SOP
//====================================================================

#include "2410addr.h"
#include "2410lib.h"
#include "def.h"
#include "2410iis.h"
#include "MDT_System.h"

void ChangeDMA2(void);
void IIS_PortSetting(void);
void __irq DMA2_Done(void);


//#define PLAY    0
//#define RECORD  1


#define PollMode    0           //1: Polling Mode
//#define DMA2Mode    1           //1: DMA2 Mode

unsigned char  *Buf,*_temp;

volatile unsigned int size = 0;
volatile unsigned int   fs = 0;
volatile char    which_Buf = 1;
unsigned short *txdata;

//------------------------------------------------------------------------------
//      SMDK2410 IIS Configuration
// GPB4 = L3CLOCK, GPB3 = L3DATA, GPB2 = L3MODE
// GPE4 = I2SSDO,  GPE3 = I2SSDI, GPE2 = CDCLK, GPE1 = I2SSCLK, GPE0 = I2SLRCK  
//------------------------------------------------------------------------------


//*********************[ Test_Iis ] *********************************
void Test_Iis(void)
{
    unsigned int i;

//    Uart_TxEmpty(0);
    txdata = (unsigned short *)0x30400000;
//    txdata = (unsigned short *)0x08000000;
    
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0x96,0x5,0x1);  //FCLK=135.428571MHz (PCLK=33.857142MHz)

    Uart_Init(33857142,115200);    
    
    mdt_printf("[ IIS test (Play) using MXIC MX92U832 CODEC ]\n");
    
//    save_B  = rGPBCON;       
//    save_E  = rGPECON;       
//    save_PB = rGPBUP;
//    save_PE = rGPEUP;

    IIS_PortSetting();

//    pISR_DMA2  = (unsigned)DMA2_Done;

//    rINTMSK    &= ~(BIT_DMA2);   

    Buf   = (unsigned char *)0x30400000;
//    Buf   = (unsigned char *)0x08000000;
    i=0;
    while(1)
    {
    	if((*(Buf + i) == 'd') && (*(Buf + i + 1) == 'a') && (*(Buf + i + 2) == 't') && (*(Buf + i + 3) == 'a'))
    	{
    		i += 4;
    		break;
	}
	i++;
    }

    size = *(Buf + i) | *(Buf + i + 1)<<8 | *(Buf + i + 2)<<16 | *(Buf + i + 3)<<24;
    size = (size>>1)<<1;

    fs   = *(Buf + 0x18) | *(Buf + 0x19)<<8 | *(Buf + 0x1a)<<16 | *(Buf + 0x1b)<<24;
    i += 4;
    mdt_printf("Sample Size = 0x%x\n",size/2);
    mdt_printf("Sampling Frequency = %d Hz\n",fs);
    mdt_printf("\n[ Now play the wave file .....]\n");
// MDT SG Initial IIS
//    mdt_SG_DeviceControl(MDT_POWERMANAGEMENT,0x01,0,0);//set Power On
//    mdt_SG_DeviceControl(MDT_ANALOG_SWITCH,0x90,0,0);//set Analog Switch, Enable HP And SP
//    Delay(500);
//    mdt_SG_DeviceControl(MDT_HP_VOLUME,0x0,0x1f,0x1f);//set HP Volume
//    mdt_SG_DeviceControl(MDT_SP_VOLUME,0x1f,0,0);//set SP Volume
//    SGWrite(0x76,0x0c);
    
#ifdef DMA2Mode   
      //DMA2 Initialize
//    rDISRC2  = (int)(Buf + 0x30);               //0x31000030~(Remove header)      
    rDISRC2  = (int)(Buf + i);               //0x31000030~(Remove header)      
    rDISRCC2 = (0<<1) + (0<<0);                 //The source is in the system bus(AHB), Increment      
    rDIDST2  = ((U32)rIISFIFO);                  //IISFIFO    
    rDIDSTC2 = (1<<1) + (1<<0);                 //The destination is in the peripheral bus(APB), Fixed  
    rDCON2   = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/4);
      //1010 0000 1001 xxxx xxxx xxxx xxxx xxxx
      //Handshake[31], Sync PCLK[30], CURR_TC Interrupt Request[29], Single Tx[28], Single service[27], 
      //I2SSDO[26:24], DMA source selected[23],Auto-reload[22], Half-word[21:20], size/2[19:0]
      
    rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0);          //No-stop[2], DMA2 channel On[1], No-sw trigger[0] 
#endif
      //IIS Initialize
    if(fs==44100)               //11.2896MHz(256fs)
        //rIISPSR = (5<<5) + 5;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)     33868800HZ
       rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)     33868800HZ
    else if(fs == 22050)                       //fs=22050, 5.6448MHz(256fs)
        rIISPSR = (5<<5) + 5;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    else if(fs == 8000)  
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xa4,0x5,0x1);  //FCLK=147.428571MHz (PCLK=36.85MHz)

    Uart_Init(36850000,115200);    
    	
        rIISPSR = (17<<5) + 17;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    	}
    else if(fs == 11025)                       
        rIISPSR = (11<<5) + 11;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    else if(fs == 16000)      
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xa4,0x5,0x1);  //FCLK=147MHz (PCLK=36.85MHz)

    Uart_Init(36850000,115200);    

	rIISPSR = (8<<5) + 8;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    	}
    else if(fs == 32000)                       
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xb7,0x5,0x1);  //FCLK=163.714825MHz (PCLK=40.928571MHz)

    Uart_Init(40928571,115200);    

        rIISPSR = (4<<5) + 4;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    	}
    else if(fs == 48000)                       
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xa4,0x5,0x1);  //FCLK=147MHz (PCLK=36.85MHz)

    Uart_Init(36850000,115200);    

        rIISPSR = (2<<5) + 2;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    	}
#ifdef DMA2Mode           
    rIISCON = (1<<5) + (1<<2) + (1<<1);         //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
      //Master mode[8],Tx mode[7:6],High for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
    rIISMOD = (0<<8) + (2<<6) + (1<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
    
    rIISFCON = (1<<15) + (1<<13);        //Tx DMA,Tx FIFO --> start piling....

    mdt_printf("\nPress any key to exit!!!\n");
    
      //IIS Tx Start
    rIISCON |= 0x1;             //IIS Interface start
    while(!Uart_GetKey());
    {
        if((rDSTAT2 & 0xfffff) < (size/6))
            ChangeDMA2();
    }
#endif
#ifdef PollMode
      //IIS Initialize
      //Master mode[8],Tx mode[7:6],High for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
    rIISMOD = (0<<8) + (2<<6) + (1<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);

    rIISFCON = (0<<15) + (1<<13);       //Tx Normal[15],Tx FIFO Enable[13] --> start piling....  
      //Tx DMA disable[5],Rx DMA disable[4],Tx not idle[3],Rx idle[2],prescaler enable[1],stop[0]
    rIISCON  = (0<<5) + (0<<4) + (0<<3) + (1<<2) + (1<<1) + (0<<0);            
   
      //Tx start
    rIISCON |=0x1;
    txdata = (unsigned short *)(0x30400000 + i);
//    txdata = (unsigned short *)(0x08000000 + i);
    
//    for(i=0;i<(size/2);i++)
//    {
//        while( (rIISCON & 0x080) == 0x80 );     //wait when fifo is not empty.
//        *rIISFIFO = *(txdata+i);                 // put the data into fifo        
//    }
#endif

}

void Test_iis_pcm(unsigned int sample_rate)
{

//    Uart_TxEmpty(0);
    
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0x96,0x5,0x1);  //FCLK=135.428571MHz (PCLK=33.857142MHz)

    Uart_Init(33857142,115200);    
    
    mdt_printf("[ IIS test (Play) using MXIC MX92U832 CODEC ]\n");

    IIS_PortSetting();

    mdt_printf("Sampling Frequency = %d Hz\n",sample_rate);
      //IIS Initialize
    if(sample_rate==44100)               //11.2896MHz(256fs)
       rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)     33868800HZ
       //rIISPSR = (5<<5) + 5;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)     33868800HZ
    else if(sample_rate == 22050)                       //fs=22050, 5.6448MHz(256fs)
        rIISPSR = (5<<5) + 5;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    else if(sample_rate == 8000)  
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xa4,0x5,0x1);  //FCLK=147.428571MHz (PCLK=36.85MHz)

    Uart_Init(36850000,115200);    
    	
        rIISPSR = (17<<5) + 17;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    	}
    else if(sample_rate == 11025)                       
        rIISPSR = (11<<5) + 11;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)  
    else if(sample_rate == 16000)      
    	{
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0xa4,0x5,0x1);  //FCLK=147MHz (PCLK=36.85MHz)

    Uart_Init(36850000,115200);