sysfei82557end.c

intel xscale 425的bsp源码

        pciConfigInByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                         PCI_CFG_DEV_INT_LINE, &irq);

        membaseCsr   &= PCI_MEMBASE_MASK;
        iobaseCsr    &= PCI_IOBASE_MASK;
        membaseFlash &= PCI_MEMBASE_MASK;

        /* overwrite the resource table with read value */

        pReso->membaseCsr   = membaseCsr + CPU_PCI_MEM_ADRS;
        pReso->iobaseCsr    = iobaseCsr + CPU_PCI_MEM_ADRS;
        pReso->membaseFlash = membaseFlash + CPU_PCI_MEM_ADRS;
        pReso->irq          = irq;

#ifndef PCI_IO_ADRS_OK
        pReso->iobaseCsr    = pReso->membaseCsr;
#endif /*PCI_IO_ADRS_OK*/

        /* enable mapped memory and IO addresses */

        pciConfigOutWord (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                          PCI_CFG_COMMAND, PCI_CMD_IO_ENABLE |
                          PCI_CMD_MEM_ENABLE | PCI_CMD_MASTER_ENABLE);
        feiUnits++;
        }

    if(feiUnits)
        { /* one or more devices were found */
        for(unit = 0, ix = 0; unit < feiUnits && ix < MAX_END_DEVS; ++ix)
            {
            if(pendDevTbl[ix].endLoadFunc == sysFei82557EndLoad ||
               pendDevTbl[ix].endLoadFunc == END_TBL_END)
                {
                pendDevTbl[ix].unit = unit;
                pendDevTbl[ix].endLoadFunc = sysFei82557EndLoad;
                pendDevTbl[ix].endLoadString = FEI_LOAD_STRING;
                pendDevTbl[ix].endLoan = FEI_BUFF_LOAN;
                pendDevTbl[ix].pBSP = NULL;
                pendDevTbl[ix].processed = FALSE;
                ++unit;
                }
            }
        }


    /* specify the interrupt connect/disconnect routines to be used */

    feiEndIntConnect = (FUNCPTR) sys557IntConnect;
    feiEndIntDisconnect = (FUNCPTR) sys557IntDisconnect;
    }

/*******************************************************************************
*
* sys557Init - prepare LAN adapter for 82557 initialization
*
* This routine is expected to perform any adapter-specific or target-specific
* initialization that must be done prior to initializing the 82557.
*
* The 82557 driver calls this routine from the driver attach routine before
* any other routines in this library.
*
* This routine returns the interrupt level the <pIntLvl> parameter.
*
* ERRNO: N/A
*
* RETURNS: OK or ERROR if the adapter could not be prepared for initialization.
*/

STATUS sys557Init
    (
    int unit,                   /* unit number */
    FEI_BOARD_INFO *pBoard      /* board information for the end driver */
    )
    {
    FEI_RESOURCE *pReso = &feiResources [unit];
    UINT16 sum = 0;
    int ix;
    int iy;
    UINT16 value;
    void *testbuf = 0; /* keep compiler quiet */

    if (unit >= feiUnits)
        {
        return (ERROR);
        }

    /*
     * Locate the 82557 based adapter - PRO100B, INBUSINESS and XXX.
     * Note that since the INBUSINESS adapter is based upon the PRO100B
     * board type, it is initialised and driven like one.
     */

    if (pReso->boardType  != UNKNOWN)   /* only setup once */
        {
        }
    else
        {
        /* read the configuration in EEPROM */

#ifdef PCI_END_DEBUG
        printf("RFD_SIZE = 0x%x\n",RFD_SIZE);
        printf("CFD_SIZE    = 0x%x\n",CFD_SIZE); 
        printf("TOTAL FEI STORAGE: 0x%x\n",(UINT32)FEI_TOTAL_SIZE);
#endif
        for (ix = 0; ix < EE_SIZE; ix++)
            {
            value = sys557eepromRead (unit, ix);
            pReso->eeprom[ix] = value;
            sum += value;
#ifdef PCI_END_DEBUG
            printf("%4.4x ", value);
            if(ix % 4 ==0)
                {
                printf("\n");
                }
#endif
            }

        if (sum != EE_CHECKSUM)
            printf ("i82557(%d): Invalid EEPROM checksum %#4.4x\n", unit, sum);
#ifdef PCI_END_DEBUG
        else
            printf ("i82557(%d): EEPROM checksum %#4.4x\n", unit, sum);
#endif

        /* DP83840 specific setup */

        if (((pReso->eeprom[6]>>8) & 0x3f) == DP83840)
            {
            int reg23 = sys557mdioRead (unit, pReso->eeprom[6] & 0x1f, 23);
            sys557mdioWrite (unit, pReso->eeprom[6] & 0x1f, 23, reg23 | 0x0420);
            }

        /* Perform a system self-test:
         *  1) alloc some temporary 16-bit aligned memory for results
         *  2) reset the chip
         *  3) Issue SCB_PORT command
         *  4) Wait for memory to change (or timeout)
         *  5) free temporary memory
         */
        pReso->timeout = 16000;         /* Timeout for self-test. */

        /*
         * No specific area specified, so we assume that cacheDmaMalloc() will
         * return a pointer to a suitable area. If the data cache is on,
         * this will be page-aligned, but if the data cache is off, then we
         * will just get whatever malloc returns.
         */

        if (testbuf = cacheDmaMalloc (32), testbuf == 0)
            {
            printf("fei%d cacheDmaMalloc failed\n", unit);
            return ERROR;
            }
        pReso->pResults = (volatile INT32 *)testbuf;

        /* The chip requires the results buffer to be 16-byte aligned. */

        pReso->pResults = (volatile INT32 *)
            ((((int) pReso->pResults) + 0xf) & ~0xf);

        /* initialize results buffer */

        pReso->pResults[0] = 0;
        pReso->pResults[1] = -1;

        /* Convert to PCI addressing */
        if(sysPhysToPci((void*)pReso->pResults) == NULL)
        {
            printf("pReso->pResults does not reside in an area"
                   " that the PCI devices can access\n");
        }

        /*reset the chip*/
        sysPciOutLong (pReso->membaseCsr + SCB_PORT, 0x0);
        sysMicroDelay(PCI_CONFIG_DELAY);

        /* Issue the self-test command */

        /*
         * If using cacheDmaMalloc() it will return a "low-alias" address in
         * SDRAM, and this will need converting to a "high-alias"
         * address, so it can be accessed from the PCI bus.
         */

        sysPciOutLong (pReso->membaseCsr + SCB_PORT,
                      ((UINT32)sysPhysToPci((void*)pReso->pResults) | 1));

        /* wait for results */

        do
            {
            /* cause a delay of at least an I/O cycle */
            sysMicroDelay(PCI_CONFIG_DELAY);
            }
        while ((pReso->pResults[1] == -1) && (--pReso->timeout >= 0));

        if (pReso->timeout < 0)
        {               /* Test optimized out. */
            printf ("%s: Self test failed, status 0x%8.8x:\n"
                    " Failure to initialize the 82557.\n"
                    " Verify that the card is a bus-master capable slot.\n",
                    "sys557Init",
                    pReso->pResults[1]);
        }
        else
        {
#ifdef PCI_END_DEBUG
            printf ("General self-test: %s.\n"
                    " Serial sub-system self-test: %s.\n"
                    " Internal registers self-test: %s.\n"
                    " ROM checksum self-test: %s (%#8.8x).\n",
                    pReso->pResults[1] & 0x1000 ? "failed" : "passed",
                    pReso->pResults[1] & 0x0020 ? "failed" : "passed",
                    pReso->pResults[1] & 0x0008 ? "failed" : "passed",
                    pReso->pResults[1] & 0x0004 ? "failed" : "passed",
                    pReso->pResults[0]);
#endif
        }

        /* Save results so we can refer to them again later */

        pReso->str[0] = pReso->pResults[0];
        pReso->str[1] = pReso->pResults[1];

        cacheDmaFree (testbuf);

        pReso->pResults = pReso->str;

        pReso->boardType = TYPE_PRO100B_PCI;
        }

    /* initializes the board information structure */

    pBoard->vector        = pReso->irq;
    pBoard->baseAddr      = pReso->membaseCsr;

    for (ix = 0, iy = 0; ix < 3; ix++)
        {
        pBoard->enetAddr[iy++] = pReso->eeprom[ix] & 0xff;
        pBoard->enetAddr[iy++] = (pReso->eeprom[ix] >> 8) & 0xff;
        }

    pBoard->intEnable     = sys557IntEnable;
    pBoard->intDisable    = sys557IntDisable;
    pBoard->intAck        = sys557IntAck;

    /* install address conversion routines for driver
     The fei driver needs these to figure out what addresses it needs to 
    tell the nic to write to (PCI addresses) in order to access the appropriate
    areas of the AHB*/

    pBoard->sysLocalToBus = sys557EndPhysToPci;
    pBoard->sysBusToLocal = sys557EndPciToPhys;

#ifdef FEI_10MB
    pBoard->phySpeed      = NULL;
    pBoard->phyDpx        = NULL;
#endif

    return (OK);
    }

/*******************************************************************************
*
* sys557IntAck - acknowledge an 82557 interrupt
*
* This routine performs any 82557 interrupt acknowledge that may be
* required.  This typically involves an operation to some interrupt
* control hardware.
*
* This routine gets called from the 82557 driver's interrupt handler.
*
* This routine assumes that the PCI configuration information has already
* been setup.
*
* ERRNO: N/A
*
* RETURNS: OK, or ERROR if the interrupt could not be acknowledged.
*/

LOCAL STATUS sys557IntAck
    (
    int unit            /* unit number */
    )
    {
#if 0 /* No work is required for any of the supported adaptors */
    FEI_RESOURCE * pReso = &feiResources [unit];

    switch (pReso->boardType)
        {
        case TYPE_PRO100B_PCI:          /* handle PRO100B LAN Adapter */
        case TYPE_INBUSINESS_PCI:
        case TYPE_XX82559ER_PCI:
            /* no addition work necessary for the PRO100B */
            break;

        default:
            return (ERROR);
        }
#endif /* 0 */

    return (OK);
    }

/*******************************************************************************
*
* sys557eepromRead - read a word from the 82557 EEPROM
*
* This routine reads from the FEI's EEPROM:
*  1) enable EEPROM
*  2) write the READ opcode
*  3) specify the location
*  4) read the data
*  5) disable the EEPROM
*
* ERRNO: N/A
*
* RETURNS: the EEPROM data word read in.
*/

UINT16 sys557eepromRead
    (
    int unit,           /* unit number */
    int location        /* address of word to be read */
    )
    {

    UINT32 membase = feiResources[unit].membaseCsr;
    UINT32 retval = 0;
    UINT32 dataval;
    volatile UINT32 dummy;
    int ix;

    sysPciOutWord (membase + SCB_EEPROM, EE_CS);    /* enable EEPROM */

    /* write the READ opcode */

    for (ix = EE_CMD_BITS - 1; ix >= 0; ix--)
        {
        dataval = (EE_CMD_READ & (1 << ix)) ? EE_DI : 0;
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | dataval);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        }

    /* write the location */

    for (ix = EE_ADDR_BITS - 1; ix >= 0; ix--)
        {
        dataval = (location & (1 << ix)) ? EE_DI : 0;
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | dataval);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | dataval | EE_SK);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | dataval);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        dummy = sysPciInWord (membase + SCB_EEPROM);
        }

    if ((dummy & EE_DO) == 0)           /* dummy read */
        ;

    /* read the data */

    for (ix = EE_DATA_BITS - 1; ix >= 0; ix--)
        {
        sysPciOutWord (membase + SCB_EEPROM, EE_CS | EE_SK);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        retval = (retval << 1) |
                 ((sysPciInWord (membase + SCB_EEPROM) & EE_DO) ? 1 : 0);
        sysPciOutWord (membase + SCB_EEPROM, EE_CS);
        sysMicroDelay (1000);    /* delay for one IO READ cycle */
        }

    sysPciOutWord (membase + SCB_EEPROM, 0x00);     /* disable EEPROM */

    return (retval);
    }

/*******************************************************************************
*
* sys557eepromDump - dump EEPROM contents for unit
*