config.h

intel xscale 425的bsp源码

/* config.h - IXP425 Eval board configuration header */

/* Copyright 2002 Wind River Systems, Inc. */

/*
modification history
--------------------
2007-04-29 15:16 改为通过第一个串口调试,第二块flash定义从sysTffs.c内移到这里 INCLUDE_FLASH_NO2 
2006-10-18 16:09 网络和tffs都调试通过，启动后，可以通过target Shell 运行sysTffsFormat格式化flash；
01w,19oct04,m_h  CSR_BASE error
01v,22sep04,m_h  OSAL and IXP400 Release 1.5, wireless, USB
01u,17may04,vf   Added INCLUDE_IXCRYPTO option
01t,09apr04,vf   Bumped version to 9.  Removed redundant clock macros.  Added
		 ethDB macro.  Added VTS section.
01s,20nov03,m_h  Version number 1.2/8, spelling typos
01r,12aug03,m_h  polled RFC 2233
01q,31jul03,m_h  Remove references to Intel's previous naming convention
01p,21jul03,m_h  default NVRAM to EEPROM
01o,15jul03,m_h  NVRAM FLASH
01n,03jul03,m_h  LED enable macro moved here
01m,02jul03,m_h  little endian support
01k,27feb03,jb3  add C++ protection
01j,14nov02,jb3  bump decimalrev
01i,17oct02,jb  Bump rev
01h,07oct02,jb  Remove IP address size change
01g,18sep02,jb  Increasing ixEth block counts
01f,18sep02,jb  Enable ixEthAccEnd
01e,14aug02,jb  Continuing End support and changing sdram from 128MB to 256MB
01d,26jun02,jb  Adding ixp425 End support
01c,18jun02,jb  Changing BOARD_DESC
01b,12jun02,jb  Continuing restructure
01a,05jun02,jb  initial version...
*/

/*
This module contains the configuration parameters for ixp425 IXDP425 platform.
*/


#ifndef INCconfigh
 #define INCconfigh

#ifdef __cplusplus
extern "C" {
#endif


/** BSP version/revision identification, before configAll.h **/

 #define BSP_VER_1_2     1	/* 1.2 is backward compatible with 1.1 */
 #define BSP_VER_1_1	 1	
 #define BSP_VERSION	 "1.2"	/* Tornado 2.2 is 1.2 */
 #define BSP_REV	 "/10"	/* 0 for first revision */

#if _BYTE_ORDER == _BIG_ENDIAN
 #define BOARD_DESC	"Intel IXP425 - IXDP425 BE"
#else
 #define BOARD_DESC	"Intel IXP425 - IXDP425 LE"
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

 #include "configAll.h" /* Include the default configurations */

#define INCLUDE_IXETH
#ifdef INCLUDE_IXETH
#ifdef DISPLAY_CSR_BASE_ERROR
#error You must define the environment variable CSR_BASE. This should be your Intel Access Library directory.
#endif /*DISPLAY_CSR_BASE_ERROR*/
#ifndef   _ASMLANGUAGE
 /* Detect invalid CSR_BASE early */
#include "IxTypes.h"
#endif /* _ASMLANGUAGE */

/* define this to include IxEthAcc support */
#define INCLUDE_IXETHACCEND

#endif /* INCLUDE_IXETH */

#undef INCLUDE_WINDVIEW
#undef INCLUDE_WINDVIEW_CLASS

#undef INCLUDE_MIB2_ALL

/*
 * STANDALONE_NET must be defined for network debug with
 * standalone vxWorks.st
 */
#define STANDALONE_NET

/*
 * make use of data cache for fast DRAM
 */
 #undef INCLUDE_FAST_DRAM
 #ifdef INCLUDE_FAST_DRAM
  #define FD_CACHELINE	  8		 /* 8 UINT32's in a cache line (32-bytes) */
  #define FD_LINESPERSET 28		 /* 28 available cache lines per set */
  #define FD_SETS	 32		 /* 32 sets in data cache */

  #define FD_MAX_LINES (FD_LINESPERSET * FD_SETS)      /* Max number of lines one can allocate (28 x 32) */

/*
 * Location of virtual address just above SDRAM. This must be outside everybody else's
 * address to avoid colision issues.
 */
  #define FD_ORIGIN    0x10000000	 
  #define FD_MAX_SIZE  0x7000		 /* Max size for MMU table description, 28Kbytes */

/* modify based on the number of cache lines you want to use as data ram... */
  #define FD_NUMLINES  FD_MAX_LINES	 /* set for max 28Kbytes */
 #endif /* INCLUDE_FAST_DRAM */

/* 
 * Support network devices.
 */
#define  INCLUDE_NETWORK

/* 
 * First line below indicates host (xx.xx.xx.xx) and path of image
 *  (c:\vxWorks). The parameters that follow are:
 *  h  = Internet address of host (xx.xx.xx.xx)
 *  e  = Internet address of target (xx.xx.xx.xx)
 *  tn = Name of target machine
 *  u  = user name used to access host
 *  pw = password for user
 *  o  = other
 */

#define DEFAULT_BOOT_LINE \
	  "tffs=0,0(0,0)host:/tffs0/vxWorks " \
	  "h=192.168.25.35 e=192.168.25.121 u=target pw=pass f=0x08 tn=VxTarget o=ixe"

/** Selection Macros, which might have affect later **/

 #define INCLUDE_SYS_HW_INIT_0
 #ifdef INCLUDE_SYS_HW_INIT_0
  #ifndef _ASMLANGUAGE
   IMPORT void sysHwInit0 (void);
  #endif /* _ASMLANGUAGE */
  #define SYS_HW_INIT_0() sysHwInit0 ()
 #endif /* INCLUDE_SYS_HW_INIT_0 */

 #define INCLUDE_TIMESTAMP
 #define INCLUDE_USER_TIMESTAMP

#define SYS_CLK_RATE_MIN (10)	  /* Minimum rate at which the system clock can run */
#define SYS_CLK_RATE_MAX (1000)	  /* 1000 ticks, Maximum rate at which the system clock can run */

#define AUX_CLK_RATE_MIN (10)	  /* Minimum rate at which the auxiliary clock can run */
#define AUX_CLK_RATE_MAX (1000)	  /* 1000 ticks, Maximum rate at which the auxiliary clock can run */

 #ifdef INCLUDE_USER_TIMESTAMP
  #define USER_TIMESTAMP      sysTimestamp
  #define USER_TIMESTAMPLOCK  sysTimestampLock
  #define USER_TIMEENABLE     sysTimestampEnable
  #define USER_TIMEDISABLE    sysTimestampDisable
  #define USER_TIMECONNECT    sysTimestampConnect
  #define USER_TIMEPERIOD     sysTimestampPeriod
  #define USER_TIMEFREQ	      sysTimestampFreq
 #endif	 /* INCLUDE_USER_TIMESTAMP */

 #define INCLUDE_EXC_HANDLING
 #define INCLUDE_EXC_TASK

 #define INCLUDE_RAM_PAGE_TABLE

 #undef INCLUDE_IXP425_UART_DEBUG /* Turn off very low level debug */

 #define INCLUDE_UART1_SUPPORT /* Include Uart 1 console support  */
 #define INCLUDE_UART2_SUPPORT /* Include Uart 2 console support  */

/* Use this define to enable/disable writing to the LED display */
#define INCLUDE_IXDP425_LED_DEBUG


#define INCLUDE_WDB

/*** UART ***/
/*
 * Since there are two UARTs. The default UART defs like NUM_TTY, CONSOLE_TTY
 * and CONSOLE_BAUD_RATE in configAll.h should work fine. If you change any
 * defaults, it might affect the WDB defs also, so cross check with WDB defs.
 *
*/
 #define N_UARTS	   2	    /* Enable both uarts */
 #undef	 NUM_TTY
 #define NUM_TTY	   N_UARTS
 #define DEFAULT_BAUD	   9600
 #define UART_DEFAULT_BAUD 9600

 #undef	 CONSOLE_TTY
 #define CONSOLE_TTY	   0			/* 1 change 0 by luhb */

#if 0
 #undef	 CONSOLE_BAUD_RATE
 #define CONSOLE_BAUD_RATE DEFAULT_BAUD

#undef WDB_TTY_CHANNEL
#define WDB_TTY_CHANNEL		0	/* default Sio SERIAL channel */

#undef WDB_TTY_DEV_NAME
#define WDB_TTY_DEV_NAME    "/tyCo/0"	/* default TYCODRV_5_2 device name */

#endif

/*
 * Define SERIAL_DEBUG to enable Windriver debugging
 * via the serial ports.
 */
 #undef SERIAL_DEBUG

#ifdef INCLUDE_WDB
 #ifdef SERIAL_DEBUG
  #define WDB_NO_BAUD_AUTO_CONFIG

  #undef WDB_COMM_TYPE
  #undef WDB_TTY_BAUD
  #undef WDB_TTY_CHANNEL
  #undef WDB_TTY_DEV_NAME

  #define WDB_COMM_TYPE		  WDB_COMM_SERIAL /* WDB in Serial mode */
  #define WDB_TTY_BAUD		  9600	  /* Baud rate for WDB Connection */
  #define WDB_TTY_CHANNEL	  0		  /* COM PORT #2 */
  #define WDB_TTY_DEV_NAME	  "/tyCo/1"	  /* default TYCODRV_5_2 device name /tyCo/1 by luhb*/
 #else /* SERIAL_DEBUG */
  /* Network WDB engine. */
 #endif /* SERIAL_DEBUG */
#endif /* INCLUDE_WDB */

/*** MMU ***/
 #define INCLUDE_MMU_BASIC

 #ifdef INCLUDE_MMU_FULL  /* Full MMU Configuration */
  #undef INCLUDE_MMU_BASIC
 #endif /* INCLUDE_MMU_FULL */

 #ifdef INCLUDE_MMU_BASIC /* Basic MMU Configuration */
  #undef INCLUDE_MMU_FULL
 #endif /* INCLUDE_MMU_BASIC */

 #if defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_BASIC)
  #define INCLUDE_MMU_VIRTUAL_MEM_EQUAL_PHY_MEM  /* Provide BSP mmuPhysToVirt,mmuVirtToPhys linear 1:1 mapping */
 #endif /* INCLUDE_MMU_FULL || INCLUDE_MMU_BASIC */

/***************************** 
 * Cache  support 
 ******************************/
 #define INCLUDE_CACHE_SUPPORT

/* StrongARM I-cache mode is a bit of an inappropriate concept, but use this */
 #undef	 USER_I_CACHE_MODE
 #define USER_I_CACHE_MODE	 CACHE_WRITETHROUGH

/* StrongARM has to be this, as it does not support writethrough */
 #undef	 USER_D_CACHE_MODE
 #define USER_D_CACHE_MODE	 CACHE_COPYBACK

/* When running in LE mode we always want to enable the MMU.
 * If a big endian build is to enable the MMU in the ROM then
 * the following byte order check should be removed */
#if (_BYTE_ORDER == _LITTLE_ENDIAN)
#define ROM_ENABLES_MMU
#else
#undef ROM_ENABLES_MMU
#endif /* _BYTE_ORDER == _LITTLE_ENDIAN */

#ifdef ROM_ENABLES_MMU

/*
 * if you def/undef the SECOND_LEVEL_PAGE_TABLE, you need to change the
 * ROM_TEXT_ADRS in the Makefile. see #define ROM_TEXT_ADRS
 */
 #undef SECOND_LEVEL_PAGE_TABLE	 /* selected the two level table */

 #if defined(SECOND_LEVEL_PAGE_TABLE)
  #define MMU_TABLE_SIZE     0x4800
 #else
  #define MMU_TABLE_SIZE     0x4000
 #endif /* SECOND_LEVEL_PAGE_TABLE */

#endif /* ROM_ENABLES_MMU */

 #if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
  #define INCLUDE_MMU
 #endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */

 #undef VM_PAGE_SIZE
 #define VM_PAGE_SIZE		4096

/* Memory configuration */
#undef LOCAL_MEM_AUTOSIZE		    		/* NO run-time memory sizing */
#define LOCAL_MEM_LOCAL_ADRS	0x00000000  		/* The start of on board memory area */ 
#define LOCAL_MEM_SIZE		(64 * 0x00100000) 	/* 256Meg - amount of memory for VxWorks  - all */ 
#define USER_RESERVED_MEM	(4 *  0x00100000)   	/* 4Meg for now */


/*** RAM Information ***/
/* Link Address: To where the bootrom image will be decompressed  into reserved memory at top of memory*/
#define RAM_HIGH_ADRS           0x02000000		/* 32MB - This must be the same as in Makefile */
/* RAM starting address, RAM Size */
#define RAM_LOW_ADRS            0x00010000  /* VxWorks image entry point */ 

/* Some sanity checking on defined Memory values and considerations on how
 * these will affect the ROM MMU table */ 
#ifdef ROM_ENABLES_MMU

#ifdef LOCAL_MEM_AUTOSIZE
#error "The bootrom MMU translation table inromInit.s does not use autosizing and will have unpredictable behaviour if this is defined"
#endif

#if (LOCAL_MEM_LOCAL_ADRS != 0x00000000)
#error "The bootrom MMU translation table assumes that SDRAM starts at 0x0"
#endif

#if (LOCAL_MEM_SIZE > (256 * 0x00100000))
#error "The bootrom MMU translation table assumes that SDRAM max size is <= 256 Meg"
#endif

#endif /* ROM_ENABLES_MMU */


/*
 * Boot ROM is an image written into Flash ROM and started
 * at address 0. Due to the remapping of memory by the internal BUS
 * controller , the Flash memory appears at an address of 0x50000000.
 *
 * The following parameters are defined here and in the Makefile.
 * They must be kept synchronized; effectively config.h depends on
 * Makefile. Any changes made here must be made in the Makefile and vice
 * versa.
 *
 * ROM_BASE_ADRS is the base of the Flash ROM
 * ROM_TEXT_ADRS is the entry point of the VxWorks image
 * ROM_SIZE is the size of the part of the Flash ROM allocated to the VxWorks
 *          image (block size - size of headers - NVRAM allocation)
 *
 * Two other constants are used:
 * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
 *       (uncompressed bootrom)
 * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
 *
 * The boot ROM image starts at an offset of 0 into the n'th block of flash
 * to give the diagnostics and other RTOS's room to live in.
 *
 * So the calculation for ROM_TEXT_ADRS is:
 *                         Virtual      Physical
 *   Address of Flash:     0x50000000   0x50000000
 *   Offset of nth block:  0x00000000   0x00000000  - Currently putting Bootrom at offset zero into flash 
 *   Sum:                  0x50000000   0x50000000
 *
 * Note also that the addresses given here are virtual addresses after
 * the MMU is turned on. The physical addresses will be based on zero.
 *
 * The values are given as literals here to make it easier to ensure
 * that they are the same as those in the Makefile. The build of the bootrom
 * will check that it does not overflow the space allocated.
 */

#define ROM_FLASH_BASE      	(0x50000000) 	/* Base address of CS0 in boot position */
#define ROM_FLASH_ALT_BASE      (0x50000000) 	/* Base address of CS0 in alternate position */
#define ROM_FLASH_OFFSET    	(0x0) 		/* Offset in Flash dedicated to VxWorks BSP */
/*#define ROM_FLASH_RESERVED	(0* 0x00100000)	*/	/* Size of Flash dev reserved from top */