ixethaccend.c

intel xscale 425的bsp源码

        goto errorExit;
        }
        
    /* 
     * Set the RFC2233 flag bit in the END object flags field and
     * install the counter update routines.
     */

    m2IfPktCountRtnInstall(pDrvCtrl->end.pMib2Tbl, m2If8023PacketCount);

    /*
     * Make a copy of the data in mib2Tbl struct as well. We do this
     * mainly for backward compatibility issues. There might be some
     * code that is referencing the END pointer and doing lookups on
     * the mib2Tbl, which will cause all sorts of problems.
     */

    bcopy ((char *)&pDrvCtrl->end.pMib2Tbl->m2Data.mibIfTbl,
                   (char *)&pDrvCtrl->end.mib2Tbl, sizeof (M2_INTERFACETBL));

    endObjFlags = IFF_NOTRAILERS | IFF_BROADCAST | END_MIB_2233;

#else /* INCLUDE_RFC_2233 */

    if (END_MIB_INIT (&pDrvCtrl->end, M2_ifType_ethernet_csmacd,
                      &pDrvCtrl->enetAddr[0], 6, ETHERMTU,
                      END_SPEED)
        == ERROR)
        goto errorExit;

    endObjFlags = IFF_NOTRAILERS | IFF_BROADCAST;

#endif /* INCLUDE_RFC_2233 */

    /* Perform memory allocation/distribution */

    if (ixEthAccEndMemInit (pDrvCtrl) == ERROR)
        goto errorExit;

    /* reset and reconfigure the device */
    ixEthAccEndReset (pDrvCtrl);
    ixEthAccEndConfig (pDrvCtrl);

    /* set the flags to indicate readiness */

#ifdef IXEETHACC_MULTICAST_ENABLE
    endObjFlags |= IFF_MULTICAST;
#endif

    END_OBJ_READY (&pDrvCtrl->end, endObjFlags);

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Done loading IxEthAccEnd...",
                 1, 2, 3, 4, 5, 6);

    /* Capture pDrvCtrl */
    ixEthAccpDrvCtrl[pDrvCtrl->unit] = pDrvCtrl;
    
    return(&pDrvCtrl->end);

    errorExit:
    if (pDrvCtrl != NULL)
        {
            free ((char *)pDrvCtrl);
        }

    logMsg("IxEthAccEndLoad Failed\n", 1, 2, 3, 4, 5, 6);

    return NULL;
}

/******************************************************************************
*
* ixEthAccEndParse - parse the init string
*
* Parse the input string.  Fill in values in the driver control structure.
*
* The muxLib.o module automatically prepends the unit number to the user's
* initialization string from the BSP (configNet.h).
*
* .IP <unit>
* Device unit number, a small integer.
* .IP <vecNum>
* Interrupt vector number (used with sysIntConnect)
* .IP <intLvl>
* Interrupt level
* .LP
*
* RETURNS: OK or ERROR for invalid arguments.
*/

LOCAL STATUS ixEthAccEndParse
    (
    END_DEVICE * pDrvCtrl,  /* device pointer */
    char * initString       /* information string */
    )
{
    char*   tok;
    char*   pHolder = NULL;

    /* Parse the initString */

    /* Unit number. (from muxLib.o) */

    tok = strtok_r (initString, ":", &pHolder);
    if (tok == NULL)
        return ERROR;
    pDrvCtrl->unit = atoi (tok);

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Parsed unit number %d\n",
                 pDrvCtrl->unit , 2, 3, 4, 5, 6);

    /* Interrupt vector. */

    pDrvCtrl->ivec = 0;
    pDrvCtrl->ilevel = 0;

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Processed all arguments\n",
                 1, 2, 3, 4, 5, 6);

    return OK;
}


/******************************************************************************
*
* ixEthAccEndPoolInit - initialize pool for the device
*
* This routine is highly specific to the CSR access layers.
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS ixEthAccEndPoolInit
    (
    NET_POOL_ID * ppNetPool,   /* pool to be initialized */
    int count,                 /* number of buffers to initialize */
    int size                   /* size of buffer to initialize */
    )
{
    void *poolBufPtr;
    void *poolDataPtr;
    M_CL_CONFIG ixMbufClBlkCfg;
    CL_DESC ixMbufClDesc;
    UINT32 poolBufSize, poolDataSize;

    /* set the size of the mblk headers, the clBlk headers and the clPool
     * payload with cache line alignement constraints 
     */
    UINT32 mBlk_size = ROUND_UP((sizeof(IX_OSAL_MBUF) + sizeof(long)), 
                                _CACHE_ALIGN_SIZE);
    UINT32 cLBlk_size = ROUND_UP(CL_BLK_SZ, _CACHE_ALIGN_SIZE);
    UINT32 cLPool_size = ROUND_UP(size, _CACHE_ALIGN_SIZE);

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Pool allocation start\n",
                 1, 2, 3, 4, 5, 6);

    /* set the size of the pool of headers */
    poolBufSize = _CACHE_ALIGN_SIZE + (count *  mBlk_size) +
        _CACHE_ALIGN_SIZE + (count * cLBlk_size) + 
        _CACHE_ALIGN_SIZE;
    poolBufSize = ROUND_UP(poolBufSize, _CACHE_ALIGN_SIZE);

    /* set the size of the pool of buffers */
    poolDataSize = _CACHE_ALIGN_SIZE + (count * cLPool_size) +
        _CACHE_ALIGN_SIZE;
    poolDataSize = ROUND_UP(poolDataSize, _CACHE_ALIGN_SIZE);

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Memory needed %u + %u bytes\n",
                 poolBufSize, poolDataSize, 3, 4, 5, 6);

    /* allocate a pool */
    *ppNetPool = malloc(sizeof(NET_POOL));
    if (*ppNetPool == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, 
                     "NetPool memory allocation failed (size %u)\n", 
                     sizeof(NET_POOL), 2, 3, 4, 5, 6);
        return (ERROR);
    }

    /* fills the structures needed by netPoolInit() */
    ixMbufClBlkCfg.mBlkNum  = count;
    ixMbufClBlkCfg.clBlkNum = count;
    ixMbufClBlkCfg.memSize = poolBufSize;
    ixMbufClDesc.clSize = cLPool_size;
    ixMbufClDesc.clNum  = count;
    ixMbufClDesc.memSize = poolDataSize;

     /* allocate the memory area for the pool 
     * If the memory needed, is uncached, use the functions to
     * allocate uncached memory. However, the mbuf headers always need
     * to be aligned on a cache line boundary in CSR 1.5
     */
#ifdef IXE_CACHED_RX_BUFFERS_ENABLE

    /* return an aligned part of cached memory */
    poolBufPtr = memalign(_CACHE_ALIGN_SIZE, poolBufSize  + _CACHE_ALIGN_SIZE);
    if (poolBufPtr == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD,
                     "Mbuf memory allocation failed (size %u)\n",
                     poolBufSize, 2, 3, 4, 5, 6);

        free(*ppNetPool);
        return (ERROR);
    }

    poolDataPtr = memalign(_CACHE_ALIGN_SIZE, poolDataSize + _CACHE_ALIGN_SIZE);
    if (poolDataPtr == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD,
                     "Data memory allocation failed (size %u)\n",
                     poolDataSize, 2, 3, 4, 5, 6);

        free(*ppNetPool);
        free (poolBufPtr);
        return (ERROR);
    }

    ixMbufClBlkCfg.memArea = poolBufPtr;
    ixMbufClDesc.memArea =  poolDataPtr;

#else /* IXE_CACHED_RX_BUFFERS_ENABLE */

    /* return a part of uncached memory */
    poolBufPtr = cacheDmaAlloc(_CACHE_ALIGN_SIZE * 2 + poolBufSize);
    if (poolBufPtr == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD,
                     "Mbuf memory allocation failed (size %u)\n",
                     poolBufSize, 2, 3, 4, 5, 6);

        free (*ppNetPool);
        return (ERROR);
    }
    poolDataPtr = cacheDmaAlloc(_CACHE_ALIGN_SIZE * 2 + poolDataSize);
    if (poolDataPtr == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD,
                     "Data memory allocation failed (size %u)\n",
                     poolDataSize, 2, 3, 4, 5, 6);

        free (*ppNetPool);
        cacheDmaFree (poolBufPtr);
        return (ERROR);
    }

    /* cacheDmaMalloc does not always return an aligned part of memory.
     * As a result, the memory area is rounded up to the next cache line
     * boundary because it is necessary to ensure that the last cache line used
     * with the IX_OSAL_MBUFs will not span over an other part of memory.
     */
    ixMbufClBlkCfg.memArea = (void *)ROUND_UP(((UINT32)poolBufPtr),
                                  IX_XSCALE_CACHE_LINE_SIZE);

    ixMbufClDesc.memArea =  (void *)ROUND_UP(((UINT32)poolDataPtr),
                                   IX_XSCALE_CACHE_LINE_SIZE);
 
#endif /* IXE_CACHED_RX_BUFFERS_ENABLE */

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, 
                 "Memory allocation complete data=%x mbuf=%x\n", 
                 (unsigned)poolDataPtr, 
                 (unsigned)poolBufPtr, 3, 4, 5, 6);

    if (netPoolInit (*ppNetPool, 
                     &ixMbufClBlkCfg, 
                     &ixMbufClDesc, 
                     1, 
                     _pIxOsBufLibPoolFuncTbl) != OK)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Pool allocation failed\n",
                     1, 2, 3, 4, 5, 6);

        /* pool was not initialised successfully 
         * realease the allocated memory before leaving the function
         */
#ifdef IXE_CACHED_RX_BUFFERS_ENABLE
      free (*ppNetPool);   /* allocated from malloc */
      free (poolBufPtr);   /* allocated from memalign */
      free (poolDataPtr);  /* allocated from memalign */
#else
      free (*ppNetPool);   /* allocated from malloc */
      cacheDmaFree (poolBufPtr);  /* allocated from cacheDmaAlloc */
      cacheDmaFree (poolDataPtr); /* allocated from cacheDmaAlloc */
#endif
       return (ERROR);
    }

#ifdef IXE_CACHED_RX_BUFFERS_ENABLE
    /* flush the pool information to RAM after carving is complete.
     * 
     */
    IX_ACC_DATA_CACHE_FLUSH(poolBufPtr, poolBufSize);
    IX_ACC_DATA_CACHE_FLUSH(poolDataPtr, poolDataSize);
#endif

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, 
                 "Pool allocation complete PoolId is 0x%08x\n",
                 (unsigned)*ppNetPool, 2, 3, 4, 5, 6);

    return OK;
}


/******************************************************************************
*
* ixEthAccEndMemInit - initialize memory for the chip
*
* This routine is highly specific to the device.
*
* RETURNS: OK or ERROR.
*/

LOCAL STATUS ixEthAccEndMemInit
    (
    END_DEVICE * pDrvCtrl   /* device to be initialized */
    )
{
    /* allocate a pool of IX_OSAL_MBUF headers for Tx services
     * The size of the buffer payload is not important, but the 
     * underlying code checks that the size is at least 64
     */
    if (ixEthAccEndPoolInit(&(pDrvCtrl->pTxNetPool),
                          IXETHACC_MBLKS,
                          64+ALIGN_MLEN) 
        != OK)
    {

        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Pool init failure (1)\n",
                     1, 2, 3, 4, 5, 6);
        return(ERROR);
    }

    /* allocate a pool of IX_OSAL_MBUF for Rx services */
    if (ixEthAccEndPoolInit(&(pDrvCtrl->end.pNetPool),
                          IXETHACC_MBLKS + IXETHACC_MBLKS_RESERVED,
                          IX_ETHACC_RX_MBUF_MIN_SIZE + ALIGN_MLEN) 
        != OK)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Pool init failure (2)\n",
                     1, 2, 3, 4, 5, 6);
        return(ERROR);
    }

    /*
     * If you need clusters to store received packets into then get them
     * here ahead of time.
     */
    if ((pDrvCtrl->pClPoolId = netClPoolIdGet (pDrvCtrl->end.pNetPool,
                                               IX_ETHACC_RX_MBUF_MIN_SIZE, 
                                               FALSE))
        == NULL)
    {
        IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "netClPoolIdGet failure\n",
                     1, 2, 3, 4, 5, 6);
        return(ERROR);
    }

    /* The number of cblk/mblk pairs allocated for NPE Rx service */
    pDrvCtrl->rxBufsAlloc = IXETHACC_MBLKS;

    IXP_DRV_LOG (IXP_DRV_DEBUG_LOAD, "Memory setup complete\n",
                 1, 2, 3, 4, 5, 6);

#ifdef IXP_DRV_DEBUG
    /* allow log messages to print (1 second) */
    taskDelay(sysClkRateGet());
#endif IXP_DRV_DEBUG

    return OK;
}


/******************************************************************************
*
* Return buffers to the Intel Ethernet Engine 
*/
LOCAL __inline__ STATUS ixEthAccEndReplenish
    (
    END_DEVICE *pDrvCtrl,   /* interrupting device */
    IX_OSAL_MBUF *pIxpBuf
    )
{
    if (ixOsalFastMutexTryLock(&(pDrvCtrl->fastReplMutex)) == IX_SUCCESS)
    {
        IXP_DRV_LOG ((IXP_DRV_DEBUG_INT | IXP_DRV_DEBUG_RX), 
                     "RxFree ixe[%d] Hdr: 0x%08x Buff: 0x%08x Size: %x\n"
                     , pDrvCtrl->unit
                     , (int)pIxpBuf
                     , (int)IX_OSAL_MBUF_MDATA(pIxpBuf)