ixethaccsysend.c

intel xscale 425的bsp源码

    return(IX_SUCCESS);
    }


/**
 * @fn IX_STATUS ixdp425EthAccMacSet()
 *
 * Set the MAC address for available Ports on the board.
 * It is assumed that the MAC addresses are stored in non-volatile storage.
 *
 * @return IX_SUCCESS - MAC address successfuly set
 * @return IX_FAIL - Error setting MAC address
 */

PRIVATE IX_STATUS ixdp425EthAccMacSet(int port)
    {
    IxEthAccMacAddr npeMacAddr;

#ifdef IXDP_ETHACC_USE_NVRAM_MAC
    if (sysNvRamGet((UINT8 *)&npeMacAddr.macAddress, 
                    IX_IEEE803_MAC_ADDRESS_SIZE, 
                    nvRamNpeMacAddr[port]) == ERROR)
        {
        printf("ixe %d - Unable to read MAC address from non-volatile storage!\n"
               , port
              );
        return(IX_FAIL);
        }

    /* Check for a valid MAC address - Only compare first three bytes */
    if ( bcmp( (char *)&npeMacAddr.macAddress, ixdp425IntelMacPrefix, 3) )
        {
        /* Don't have a valid MAC in NVRAM so we fall back to Intel's base addresses */
        bcopy ((char *)sysIxEthAccEndEnetAddr, (char *)npeMacAddr.macAddress, 6);
        npeMacAddr.macAddress[5] += port;

        printf("ixe ETH PHY %d Hard Coded MAC address is: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n"
           , port
           ,npeMacAddr.macAddress[0], npeMacAddr.macAddress[1]
           ,npeMacAddr.macAddress[2], npeMacAddr.macAddress[3]
           ,npeMacAddr.macAddress[4], npeMacAddr.macAddress[5]);
        }
    else
        {
#ifdef SYS_END_DEBUG
        printf("ixe ETH PHY %d MAC address is: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n"
           , port
           ,npeMacAddr.macAddress[0], npeMacAddr.macAddress[1]
           ,npeMacAddr.macAddress[2], npeMacAddr.macAddress[3]
           ,npeMacAddr.macAddress[4], npeMacAddr.macAddress[5]);
#endif /* SYS_END_DEBUG */
        }

#else	/* Hard encoded MAC */

    bcopy ((char *)sysIxEthAccEndEnetAddr, (char *)npeMacAddr.macAddress, 6);
    npeMacAddr.macAddress[5] += port;

    printf("ixe ETH PHY %d Hard Coded MAC address is: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n"
           , port
           ,npeMacAddr.macAddress[0], npeMacAddr.macAddress[1]
           ,npeMacAddr.macAddress[2], npeMacAddr.macAddress[3]
           ,npeMacAddr.macAddress[4], npeMacAddr.macAddress[5]);

#endif 

    if (ixEthAccPortUnicastMacAddressSet(port, &npeMacAddr) != IX_ETH_ACC_SUCCESS)
        {
        return(IX_FAIL);
        }

    return(IX_SUCCESS);
    }



#ifndef INCLUDE_IXETHACC_POLL_MODE
/* task used for traffic debug (debug through interrupts
*   is not possible)
*/
static void dispatchTask(void)
{
    while (1)
    {
	taskDelay(0);
	(*dispatcherFunc) (IX_QMGR_QUELOW_GROUP);
    }
}

#endif


/**
 * @fn IX_STATUS ixdp425EthAccStartDispatch()
 *
 * @param BOOL interruptMode - start in interrupt or polled mode
 *
 * This function starts the Queue manager dispatch timer.
 * 
 * @return IX_SUCCESS - Dispatch timer successfully started
 * @return IX_FAIL - Error starting dispatch timer
 */

PRIVATE IX_STATUS ixdp425EthAccStartDispatch(BOOL interruptMode)
    {

    ixQMgrDispatcherLoopGet(&dispatcherFunc);

    if (interruptMode)   /* Interrupt mode */
        {
#ifdef SYS_END_DEBUG
        DRV_LOG("ixdp425EthAccStartDispatch: interrupt mode\n");
#endif /* SYS_END_DEBUG */

        /* 
         * Hook the QM QLOW dispatcher to the interrupt controller. 
         * The ethernet NPEs use queues 24 through 27.
         */
        if (ixOsalIrqBind(IXP425_INT_LVL_QM1,
			  (VOIDFUNCPTR)dispatcherFunc,
			  (void *)IX_QMGR_QUELOW_GROUP) != IX_SUCCESS)
            {
            printf("ixe Ethernet Lib - Failed to bind to QM1 interrupt\n"
                  );
            return(IX_FAIL);
            }
        }
    else    /* Polled mode */
        {
#ifdef INCLUDE_IXETHACC_POLL_MODE
        /* 
         * Hook the QM QLOW dispatcher to clock interrupts
	 * (best performances)
         */
        ixpAuxClkDisable();
        ixpAuxClkRateSet (IXDP_ETHACC_POLL_TICKS_PER_SECOND);
        ixpAuxClkConnect ((FUNCPTR)dispatcherFunc,
                          IX_QMGR_QUELOW_GROUP);
        ixpAuxClkEnable();
#else /* INCLUDE_IXETHACC_POLL_MODE */
        /* 
         * Run the QM QLOW dispatcher in a task
	 * (for debug purposes)
         */
	taskSpawn("QMgr",     /* Name */
		  100,        /* Priority */
		  0,          /* Options */
		  4096 * 2,   /* Stack Size */
		  (FUNCPTR)(dispatchTask),
		  0,0,0,0,0,0,0,0,0,0);
#endif /* INCLUDE_IXETHACC_POLL_MODE */
        }

    return(IX_SUCCESS);
    }


/* this function is called once at initialisation */
IX_STATUS ixdp425EthLibInit()
{  
    UINT32 phyNo;

    if (ixdp425EthLibInitialised)
        {
        printf("ixe Ethernet Lib - Ethernet driver already initialised\n");
        return(IX_SUCCESS);
        }

    /* Init ixEthAccPhyAddresses to 0xffffffff to indicate non-existent */
    for (phyNo=0; phyNo<IX_ETH_ACC_NUMBER_OF_PORTS; phyNo++)
        ixEthAccPhyAddresses[phyNo] = 0xffffffff;

#ifdef INCLUDE_IX_QMGR_LLP_DISPATCHER
    /* Write to featureCtrl that livelock prevention dispatcher is required */
    ixFeatureCtrlSwConfigurationWrite (IX_FEATURECTRL_ORIGB0_DISPATCHER,
                                       IX_FEATURE_CTRL_SWCONFIG_DISABLED);
#endif

    /* Initialise Queue Manager */
#ifdef SYS_END_DEBUG
    DRV_LOG("ixdp425EthLibInit: Initialising Queue Manager...\n");
#endif /* SYS_END_DEBUG */
    if (ixQMgrInit() != IX_SUCCESS)
        {
	logMsg("ERROR ixe Eth Lib : unable to initialize QMGR\n", 1, 2, 3, 4, 5, 6);
	return (IX_FAIL);
        }

    /* Start the Queue Manager dispatcher loop */
#ifdef INCLUDE_IXETHACC_POLL_MODE
    if (ixdp425EthAccStartDispatch(FALSE) != IX_SUCCESS)
#else /*INCLUDE_IXETHACC_POLL_MODE*/
    if (ixdp425EthAccStartDispatch(TRUE) != IX_SUCCESS)
#endif /*INCLUDE_IXETHACC_POLL_MODE*/
        {
        printf("ixdp425EthLibInit: Error starting Intel queue manager dispatch loop!\n");
        return(IX_FAIL);
        }

    /* Initialise and Start NPEs */
    if(ixNpeDlNpeInitAndStart(NPE_B_IMAGE) != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init NPE B!\n", 1, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }
 
    if(ixNpeDlNpeInitAndStart(NPE_C_IMAGE) != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init NPE C!\n", 1, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }

    /* start the NPE message handler */
    if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to start NPE Message handler!\n", 1, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }

#ifdef INCLUDE_IXETHDB
    /* Enable ethDB */
    ixFeatureCtrlSwConfigurationWrite (IX_FEATURECTRL_ETH_LEARNING, TRUE);
#else
    /* Disable ethDB */
    ixFeatureCtrlSwConfigurationWrite (IX_FEATURECTRL_ETH_LEARNING, FALSE);
#endif

    /* start access driver */
    printf("Starting EthAcc component ...\n");

    if (ixEthAccInit() != IX_ETH_ACC_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to start Ethernet Access driver!\n", 1, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }

    /* initialise the ports */
    if (ixEthAccPortInit(IX_ETH_PORT_1) != IX_ETH_ACC_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init port %d!\n",IX_ETH_PORT_1, 2, 3, 4, 5, 6 );
	return(IX_FAIL);
    }

    if (ixEthAccPortInit(IX_ETH_PORT_2) != IX_ETH_ACC_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init port %d!\n",IX_ETH_PORT_2, 2, 3, 4, 5, 6 );
	return(IX_FAIL);
    }

    /* initialise the phys */
    if (ixdp425EthAccPhyDetect() != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to detect phy\n", 1, 2, 3, 4, 5, 6);
	return(IX_FAIL);
    }

    /* initialise the phys */
    if (ixdp425EthAccPhyInit(IX_ETH_PORT_1) != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init phy for port %d\n", IX_ETH_PORT_1, 2, 3, 4, 5, 6);
	return(IX_FAIL);
    }

    if (ixdp425EthAccPhyInit(IX_ETH_PORT_2) != IX_SUCCESS)
    {
	logMsg("ERROR ixe Eth Lib : unable to init phy for port %d\n", IX_ETH_PORT_2, 2, 3, 4, 5, 6);
	return(IX_FAIL);
    }

    ixdp425EthLibInitialised = TRUE;

    return(IX_SUCCESS);
    }


/* this function is called during muxLoad */
IX_STATUS ixdp425EthLibLoad(int port)
{  
    if (ixdp425EthAccPhyConfig(port) != IX_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error PHY setup for port %d!\n", port, 2, 3, 4, 5, 6);
        return(IX_FAIL);
    }

    /* set the mac address */
    if (ixdp425EthAccMacSet(port) != IX_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error MAC setup for port %d!\n", port, 2, 3, 4, 5, 6);
        return(IX_FAIL);
    }

    /* set the FCS setup */
    if (ixEthAccPortTxFrameAppendFCSEnable(port) != IX_ETH_ACC_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error FCS setup for port %d!\n", port, 2, 3, 4, 5, 6);
        return(IX_FAIL);
    }
    
    if (ixEthAccPortRxFrameAppendFCSDisable(port) != IX_ETH_ACC_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error FCS setup for port %d!\n", port, 2, 3, 4, 5, 6);
	return(IX_FAIL);
    }

    if(ixEthAccPortPromiscuousModeClear(port) != IX_ETH_ACC_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error Promiscuous Mode Clear for port %d!\n", port, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }

    if(ixEthAccTxSchedulingDisciplineSet(port, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Error Discipline setup for port %d!\n", port, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }

    return(IX_SUCCESS);
}

/* this function is called during muxStart */
IX_STATUS ixdp425EthLibStart(int port)
{  
   /* Enable ports */
    if(ixEthAccPortEnable(port) != IX_ETH_ACC_SUCCESS)
    {
        logMsg("ERROR ixe Eth Lib : Unable to enable port %d!\n", port, 2, 3, 4, 5, 6);
	return (IX_FAIL);
    }
    return(IX_SUCCESS);
}

/* this function is called during muxStop */
IX_STATUS ixdp425EthLibStop(int port)
{  
    BOOL enabled;

#ifdef SYS_END_DEBUG
    DRV_LOG("ixdp425EthLibStop(%d)\n", port);
#endif /* SYS_END_DEBUG */

    /* check the port exists, is initialized and is enabled */
    if (ixEthAccPortEnabledQuery(port, &enabled) == IX_ETH_ACC_SUCCESS)
    {
	if (enabled)
	{
	    /* Disable port - unused MBufs will be returned */
	    if(ixEthAccPortDisable(port) != IX_ETH_ACC_SUCCESS)
	    {
		logMsg("ERROR ixe Eth Lib : unable to disable port %d\n", port, 2, 3, 4, 5, 6);
		return (IX_FAIL);
	    }
	}
    }
        
    return IX_SUCCESS;
}

/* this function is called suring muxUnload */
IX_STATUS ixdp425EthLibUnload(int port)
{  
#ifdef SYS_END_DEBUG
        DRV_LOG("ixdp425EthLibUnload(%d)\n", port);
#endif /* SYS_END_DEBUG */

    /* ensure the traffic is stopped */
    return ixdp425EthLibStop(port);
}

STATUS ixdp425EthEndMuxInit()
    {
    END_TBL_ENTRY     *pDevTbl;
    UINT32 phyNo;

    for ( pDevTbl = endDevTbl; pDevTbl->endLoadFunc != END_TBL_END; pDevTbl++ )
        ; /* Do nothing as we just want the increment */

    /* TODO - How to we tie phys ports to ixe's ?????? */
    for (phyNo=0; phyNo<IX_ETH_ACC_NUMBER_OF_PORTS; phyNo++)
        {

#ifndef INCLUDE_IXETHACC_PORT0_END
        if ( phyNo == 0 )
            continue;
#endif

#ifndef INCLUDE_IXETHACC_PORT1_END
        if ( phyNo == 1 )
            continue;
#endif

        /* Fill in the endDev entry for this device */
        pDevTbl->unit = phyNo;
        pDevTbl->endLoadFunc = ixEthAccEndLoad;
        pDevTbl->endLoadString = ixpEndLoadStr[phyNo];
        pDevTbl->endLoan = 1;
        pDevTbl->pBSP = NULL;
        pDevTbl->processed = FALSE;

        pDevTbl++;
        }

    return OK;
    }


STATUS ixdp425EthEndStartUp()
    {
    END_TBL_ENTRY     *pDevTbl;
    END_OBJ *         pCookie = NULL;
    UINT32 ixdp425EthEndMask;
    UINT8 nvImage[NV_RAM_IF_SIZE+1];
    UINT8 inetAddr[INET_ADDR_LEN];
    UINT8 nameAndUnit[32];
    UINT8 pNetDev[32];
    char *colon;
    int n = 0,index,ipaddrOk;

    sysNvRamGet(nvImage, NV_RAM_IF_SIZE, NV_RAM_IF_START_OFFSET);

    for ( pDevTbl = endDevTbl
            ; pDevTbl->endLoadFunc != END_TBL_END && n < IX_ETH_ACC_NUMBER_OF_PORTS
            ; pDevTbl++ )
        {