pwm.asm

用c8051f040做得一个程序

;/*---------------------------------------------------------------------------
;
;
;
;
; FILE NAME: C8051F060.H
; TARGET MCUs: C8051F060, F061, F062, F063
; DESCRIPTION: Register/bit definitions for the C8051F060 product family.
;
; REVISION 1.2
;
;---------------------------------------------------------------------------*/


;/*  BYTE Registers  */

P0       equ 80h; /* PORT 0 LATCH */
SP           equ 0x81; /* STACK POINTER */
DPL           equ 0x82; /* DATA POINTER LOW */
DPH           equ 0x83; /* DATA POINTER HIGH */
SFRPAGE       equ 84h; /* SFR PAGE REGISTER */
SFRNEXT      equ 85h; /* SFR PAGE REGISTER */
SFRLAST      equ 86h; /* SFR PAGE STACK ACCESS REGISTER */
PCON          equ 0x87; /* POWER CONTROL */
CPT0CN       equ 88h; /* COMPARATOR 0 CONTROL */
CPT1CN        equ 88h; /* COMPARATOR 1 CONTROL */
CPT2CN        equ 88h; /* COMPARATOR 2 CONTROL */
TCON          equ 88h; /* TIMER/COUNTER CONTROL */
CPT0MD        equ 89h; /* COMPARATOR 0 CONFIGURATION */
CPT1MD        equ 89h; /* COMPARATOR 1 CONFIGURATION */
CPT2MD        equ 89h; /* COMPARATOR 2 CONFIGURATION */
TMOD          equ 89h; /* TIMER/COUNTER MODE */
OSCICN        equ 8Ah; /* INTERNAL OSCILLATOR CONTROL */
TL0           equ 8Ah; /* TIMER/COUNTER 0 LOW */
OSCICL        equ 8Bh; /* INTERNAL OSCILLATOR CALIBRATION */
TL1           equ 8Bh; /* TIMER/COUNTER 1 LOW */
OSCXCN       equ 8Ch; /* EXTERNAL OSCILLATOR CONTROL */
TH0           equ 8Ch; /* TIMER/COUNTER 0 HIGH */
TH1          equ 8Dh; /* TIMER/COUNTER 1 HIGH */
CKCON       equ  8Eh; /* CLOCK CONTROL */
PSCTL         equ 8Fh; /* PROGRAM STORE R/W CONTROL */
P1            equ 90h; /* PORT 1 LATCH */
SSTA0         equ 91h; /* UART 0 STATUS */
SFRPGCN       equ 96h; /* SFR PAGE CONTROL REGISTER */
CLKSEL        equ 97h; /* OSCILLATOR CLOCK SELECTION REGISTER */
SCON0         equ 98h; /* UART 0 CONTROL */
SCON1         equ 98h; /* UART 1 CONTROL */
SBUF0         equ 99h; /* UART 0 DATA BUFFER */
SBUF1         equ 99h; /* UART 1 DATA BUFFER */
SPI0CFG       equ 9Ah; /* SPI CONFIGURATION */
SPI0DAT       equ 9Bh; /* SPI DATA */
P4MDOUT       equ 9Ch; /* PORT 4 OUTPUT MODE CONFIGURATION */
P5MDOUT       equ 9Dh; /* PORT 5 OUTPUT MODE CONFIGURATION */
SPI0CKR       equ 9Dh; /* SPI CLOCK RATE CONTROL */
P6MDOUT       equ 9Eh; /* PORT 6 OUTPUT MODE CONFIGURATION */
P7MDOUT       equ 9Fh; /* PORT 7 OUTPUT MODE CONFIGURATION */
P2           equ 0A0h; /* PORT 2 LATCH */
EMI0TC        equ 0A1h; /* EMIF TIMING CONTROL */
EMI0CN        equ 0A2h; /* EMIF CONTROL */
EMI0CF        equ 0A3h; /* EMIF CONFIGURATION */
P0MDOUT       equ 0A4h; /* PORT 0 OUTPUT MODE CONFIGURATION */
P1MDOUT       equ 0A5h; /* PORT 1 OUTPUT MODE CONFIGURATION */
P2MDOUT       equ 0A6h; /* PORT 2 OUTPUT MODE CONFIGURATION */
P3MDOUT       equ 0A7h; /* PORT 3 OUTPUT MODE CONFIGURATION */
IE            equ 0A8h; /* INTERRUPT ENABLE */
SADDR0        equ 0A9h; /* UART 0 SLAVE ADDRESS */
P1MDIN        equ 0ADh; /* PORT 1 INPUT MODE */
P2MDIN       equ 0AEh; /* PORT 2 INPUT MODE */
P3            equ 0B0h; /* PORT 3 LATCH */
FLACL         equ 0B7h; /* FLASH ACCESS LIMIT */
FLSCL         equ 0B7h; /* FLASH SCALE */
IP           equ 0B8h; /* INTERRUPT PRIORITY */
SADEN0        equ 0B9h; /* UART 0 SLAVE ADDRESS ENABLE */
ADC0CPT       equ 0BAh; /* ADC0 CALIBRATION POINTER */
AMX2CF        equ 0BAh; /* ADC2 ANALOG MULTIPLEXER CONFIGURATION */
ADC0CCF       equ 0BBh; /* ADC0 CALIBRATION COEFFICIENT */
AMX0SL        equ 0BBh; /* ADC0 MULTIPLEXER CHANNEL SELECT */
AMX2SL        equ 0BBh; /* ADC2 ANALOG MULTIPLEXER CHANNEL SELECT */
ADC0CF        equ 0BCh; /* ADC0 CONFIGURATION */
ADC1CF        equ 0BCh; /* ADC1 CONFIGURATION */
ADC2CF        equ 0BCh; /* ADC2 CONFIGURATION */
ADC0L         equ 0BEh; /* ADC0 DATA WORD LOW */
ADC1L         equ 0BEh; /* ADC1 DATA WORD LOW */
ADC2L         equ 0BEh; /* ADC2 DATA WORD LOW */
ADC0H         equ 0BFh; /* ADC0 DATA WORD HIGH */
ADC1H         equ 0BFh; /* ADC1 DATA WORD HIGH */
ADC2H         equ 0BFh; /* ADC2 DATA WORD HIGH */
CAN0STA       equ 0C0h; /* CAN0 STATUS */
SMB0CN        equ 0C0h; /* SMBUS CONTROL */
SMB0STA       equ 0C1h; /* SMBUS STATUS */
SMB0DAT       equ 0C2h; /* SMBUS DATA */
SMB0ADR       equ 0C3h; /* SMBUS SLAVE ADDRESS */
ADC0GTL       equ 0C4h; /* ADC0 GREATER-THAN LOW */
ADC2GTL       equ 0C4h; /* ADC2 GREATER-THAN LOW */
ADC0GTH       equ 0C5h; /* ADC0 GREATER-THAN HIGH */
ADC2GTH       equ 0C5h; /* ADC2 GREATER-THAN HIGH */
ADC0LTL       equ 0C6h; /* ADC0 LESS-THAN LOW */
ADC2LTL       equ 0C6h; /* ADC2 LESS-THAN LOW */
ADC0LTH       equ 0C7h; /* ADC0 LESS-THAN HIGH */
ADC2LTH       equ 0C7h; /* ADC2 LESS-THAN HIGH */
P4            equ 0C8h; /* PORT 4 LATCH */
TMR2CN        equ 0C8h; /* TIMER/COUNTER 2 CONTROL */
TMR3CN        equ 0C8h; /* TIMER/COUNTER 3 CONTROL */
TMR4CN        equ 0C8h; /* TIMER/COUNTER 4 CONTROL */
TMR2CF        equ 0C9h; /* TIMER/COUNTER 2 CONFIGURATION */
TMR3CF        equ 0C9h; /* TIMER/COUNTER 3 CONFIGURATION */
TMR4CF        equ 0C9h; /* TIMER/COUNTER 4 CONFIGURATION */
RCAP2L        equ 0CAh; /* TIMER/COUNTER 2 CAPTURE/RELOAD LOW */
RCAP3L        equ 0CAh; /* TIMER/COUNTER 3 CAPTURE/RELOAD LOW */
RCAP4L        equ 0CAh; /* TIMER/COUNTER 4 CAPTURE/RELOAD LOW */
RCAP2H        equ 0CBh; /* TIMER/COUNTER 2 CAPTURE/RELOAD HIGH */
RCAP3H        equ 0CBh; /* TIMER/COUNTER 3 CAPTURE/RELOAD HIGH */
RCAP4H        equ 0CBh; /* TIMER/COUNTER 4 CAPTURE/RELOAD HIGH */
TMR2L         equ 0CCh; /* TIMER/COUNTER 2 LOW */
TMR3L         equ 0CCh; /* TIMER/COUNTER 3 LOW */
TMR4L         equ 0CCh; /* TIMER/COUNTER 4 LOW */
TMR2H         equ 0CDh; /* TIMER/COUNTER 2 HIGH */
TMR3H         equ 0CDh; /* TIMER/COUNTER 3 HIGH */
TMR4H         equ 0CDh; /* TIMER/COUNTER 4 HIGH */
SMB0CR        equ 0CFh; /* SMBUS CLOCK RATE */
PSW           equ 0D0h; /* PROGRAM STATUS WORD */
REF0CN        equ 0D1h; /* VOLTAGE REFERENCE CONTROL 0 */
REF1CN        equ 0D1h; /* VOLTAGE REFERENCE CONTROL 1 */
REF2CN        equ 0D1h; /* VOLTAGE REFERENCE CONTROL 2 */
DAC0L         equ 0D2h; /* DAC0 LOW */
DAC1L         equ 0D2h; /* DAC1 LOW */
DAC0H         equ 0D3h; /* DAC0 HIGH */
DAC1H        equ 0D3h; /* DAC1 HIGH */
DAC0CN        equ 0D4h; /* DAC0 CONTROL */
DAC1CN        equ 0D4h; /* DAC1 CONTROL */
CAN0DATL      equ 0D8h; /* CAN0 DATA LOW */
DMA0CN        equ 0D8h; /* DMA0 CONTROL */
P5            equ 0D8h; /* PORT 5 LATCH */
PCA0CN        equ 0D8h; /* PCA CONTROL */
CAN0DATH      equ 0D9h; /* CAN0 DATA HIGH */
DMA0DAL       equ 0D9h; /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
PCA0MD        equ 0D9h; /* PCA MODE */
CAN0ADR       equ 0DAh; /* CAN0 ADDRESS */
DMA0DAH       equ 0DAh; /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
PCA0CPM0      equ 0DAh; /* PCA MODULE 0 MODE REGISTER */
CAN0TST       equ 0DBh; /* CAN0 TEST */
DMA0DSL       equ 0DBh; /* DMA0 DATA ADDRESS POINTER LOW BYTE */
PCA0CPM1      equ 0DBh; /* PCA MODULE 1 MODE REGISTER */
DMA0DSH       equ 0DCh; /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
PCA0CPM2      equ 0DCh; /* PCA MODULE 2 MODE REGISTER */
DMA0IPT       equ 0DDh; /* DMA0 INSTRUCTION WRITE ADDRESS */
PCA0CPM3      equ 0DDh; /* PCA MODULE 3 MODE REGISTER */
DMA0IDT       equ 0DEh; /* DMA0 INSTRUCTION WRITE DATA */
PCA0CPM4      equ 0DEh; /* PCA MODULE 4 MODE REGISTER */
PCA0CPM5      equ 0DFh; /* PCA MODULE 5 MODE REGISTER */
ACC           equ 0E0h; /* ACCUMULATOR */
PCA0CPL5      equ 0E1h; /* PCA CAPTURE 5 LOW */
XBR0          equ 0E1h; /* PORT I/O CROSSBAR CONTROL 0 */
PCA0CPH5      equ 0E2h; /* PCA CAPTURE 5 HIGH */
XBR1          equ 0E2h; /* PORT I/O CROSSBAR CONTROL 1 */
XBR2         equ 0E3h; /* PORT I/O CROSSBAR CONTROL 2 */
XBR3          equ 0E4h; /* PORT I/O CROSSBAR CONTROL 3 */
EIE1          equ 0E6h; /* EXTENDED INTERRUPT ENABLE 1 */
EIE2          equ 0E7h; /* EXTENDED INTERRUPT ENABLE 2 */
ADC0CN        equ 0E8h; /* ADC0 CONTROL */
ADC1CN        equ 0E8h; /* ADC1 CONTROL */
ADC2CN        equ 0E8h; /* ADC2 CONTROL */
P6            equ 0E8h; /* PORT 6 LATCH */
PCA0CPL2      equ 0E9h; /* PCA CAPTURE 2 LOW */
PCA0CPH2      equ 0EAh; /* PCA CAPTURE 2 HIGH */
PCA0CPL3      equ 0EBh; /* PCA CAPTURE 3 LOW */
PCA0CPH3      equ 0ECh; /* PCA CAPTURE 3 HIGH */
PCA0CPL4      equ 0EDh; /* PCA CAPTURE 4 LOW */
PCA0CPH4      equ 0EEh; /* PCA CAPTURE 4 HIGH */
RSTSRC        equ 0EFh; /* RESET SOURCE */
B             equ 0F0h; /* B REGISTER */
EIP1          equ 0F6h; /* EXTERNAL INTERRUPT PRIORITY 1 */
EIP2          equ 0F7h; /* EXTERNAL INTERRUPT PRIORITY 2 */
CAN0CN        equ 0F8h; /* CAN0 CONTROL */
DMA0CF        equ 0F8h; /* DMA0 CONFIGURATION */
P7            equ 0F8h; /* PORT 7 LATCH */
SPI0CN       equ 0F8h; /* SPI CONTROL */
DMA0CTL       equ 0F9h; /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
PCA0L         equ 0F9h; /* PCA COUNTER LOW */
DMA0CTH       equ 0FAh; /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
PCA0H         equ 0FAh; /* PCA COUNTER HIGH */
DMA0CSL       equ 0FBh; /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
PCA0CPL0      equ 0FBh; /* PCA CAPTURE 0 LOW */
DMA0CSH       equ 0FCh; /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
PCA0CPH0      equ 0FCh; /* PCA CAPTURE 0 HIGH */
DMA0BND       equ 0FDh; /* DMA0 INSTRUCTION BOUNDARY */
PCA0CPL1      equ 0FDh; /* PCA CAPTURE 1 LOW */
DMA0ISW       equ 0FEh; /* DMA0 INSTRUCTION STATUS */
PCA0CPH1      equ 0FEh; /* PCA CAPTURE 1 HIGH */
WDTCN         equ 0FFh; /* WATCHDOG TIMER CONTROL */


;/* Bit Definitions */

;/* TCON 0x88 */
TF1 bit       8Fh ;  /* TIMER 1 OVERFLOW FLAG */
TR1 bit        8Eh ;  /* TIMER 1 ON/OFF CONTROL */
TF0 bit        8Dh;  /* TIMER 0 OVERFLOW FLAG */
TR0 bit        8Ch ;  /* TIMER 0 ON/OFF CONTROL */
IE1 bit        8Bh ;  /* EXT. INTERRUPT 1 EDGE FLAG */
IT1 bit        8Ah ;  /* EXT. INTERRUPT 1 TYPE */
IE0 bit        89h ;  /* EXT. INTERRUPT 0 EDGE FLAG */
IT0 bit        88h ;  /* EXT. INTERRUPT 0 TYPE */

;/* CPT0CN 0x88 */
CP0EN bit       8Fh ;  /* COMPARATOR 0 ENABLE */
CP0OUT bit     8Eh ;  /* COMPARATOR 0 OUTPUT */
CP0RIF bit      8Dh ;  /* COMPARATOR 0 RISING EDGE INTERRUPT */
CP0FIF bit      8Ch ;  /* COMPARATOR 0 FALLING EDGE INTERRUPT */
CP0HYP1 bit     8Bh ;  /* COMPARATOR 0 POSITIVE HYSTERISIS 1 */
CP0HYP0 bit     8Ah ;  /* COMPARATOR 0 POSITIVE HYSTERISIS 0 */
CP0HYN1 bit     89h ;  /* COMPARATOR 0 NEGATIVE HYSTERISIS 1 */
CP0HYN0 bit     88h ;  /* COMPARATOR 0 NEGATIVE HYSTERISIS 0 */

;/* CPT1CN 0x88 */
CP1EN bit       8Fh ;  /* COMPARATOR 1 ENABLE */
CP1OUT bit      8Eh ;  /* COMPARATOR 1 OUTPUT */
CP1RIF bit      8Dh ;  /* COMPARATOR 1 RISING EDGE INTERRUPT */
CP1FIF bit      8Ch ;  /* COMPARATOR 1 FALLING EDGE INTERRUPT */
CP1HYP1 bit     8Bh ;  /* COMPARATOR 1 POSITIVE HYSTERISIS 1 */
CP1HYP0 bit     8Ah ;  /* COMPARATOR 1 POSITIVE HYSTERISIS 0 */
CP1HYN1 bit    89h ;  /* COMPARATOR 1 NEGATIVE HYSTERISIS 1 */
CP1HYN0 bit     88h ;  /* COMPARATOR 1 NEGATIVE HYSTERISIS 0 */

;/* CPT2CN 0x88 */
CP2EN bit       8Fh ;  /* COMPARATOR 2 ENABLE */
CP2OUT bit      8Eh ;  /* COMPARATOR 2 OUTPUT */
CP2RIF bit      8Dh ;  /* COMPARATOR 2 RISING EDGE INTERRUPT */
CP2FIF bit      8Ch ;  /* COMPARATOR 2 FALLING EDGE INTERRUPT */
CP2HYP1 bit     8Bh ;  /* COMPARATOR 2 POSITIVE HYSTERISIS 1 */
CP2HYP0 bit     8Ah ;  /* COMPARATOR 2 POSITIVE HYSTERISIS 0 */
CP2HYN1 bit     89h ;  /* COMPARATOR 2 NEGATIVE HYSTERISIS 1 */
CP2HYN0 bit     88h ;  /* COMPARATOR 2 NEGATIVE HYSTERISIS 0 */

;/* SCON0 0x98 */
SM00 bit        9Fh ;  /* UART 0 MODE 0 */
SM10 bit        9Eh ;  /* UART 0 MODE 1 */
SM20 bit        9Dh ;  /* UART 0 MULTIPROCESSOR EN */
REN0 bit        9Ch ;  /* UART 0 RX ENABLE */
TB80 bit        9Bh ;  /* UART 0 TX BIT 8 */
RB80 bit        9Ah ;  /* UART 0 RX BIT 8 */
TI0 bit         99h ;  /* UART 0 TX INTERRUPT FLAG */
RI0 bit        98h ;  /* UART 0 RX INTERRUPT FLAG */

;/* SCON1 0x98 */
S1MODE bit      9Fh ;  /* UART 1 MODE */
MCE1 bit        9Dh ;  /* UART 1 MCE */
REN1 bit        9Ch ;  /* UART 1 RX ENABLE */
TB81 bit        9Bh ;  /* UART 1 TX BIT 8 */
RB81 bit        9Ah ;  /* UART 1 RX BIT 8 */
TI1 bit         99h ;  /* UART 1 TX INTERRUPT FLAG */
RI1 bit         98h ;  /* UART 1 RX INTERRUPT FLAG */

;/* IE 0xA8 */
EA bit          0AFh ;  /* GLOBAL INTERRUPT ENABLE */
ET2  bit        0ADh ;  /* TIMER 2 INTERRUPT ENABLE */
ES0  bit        0ACh ;  /* UART0 INTERRUPT ENABLE */
ET1 bit         0ABh ;  /* TIMER 1 INTERRUPT ENABLE */
EX1 bit         0AAh ;  /* EXTERNAL INTERRUPT 1 ENABLE */
ET0 bit        0A9h ;  /* TIMER 0 INTERRUPT ENABLE */
EX0 bit         0A8h ;  /* EXTERNAL INTERRUPT 0 ENABLE */

;/* IP 0xB8 */