📄 wycunchuqibujian.rpt
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-- Node name is '|LPM_RAM_IO:1|datatri3~1~3~2'
-- Equation name is '_LC2_E8', type is buried
-- synthesized logic cell
_LC2_E8 = LCELL( _EQ007);
_EQ007 = we/rd
# !a9
# _EC1_E & _EC2_E;
-- Node name is '|LPM_RAM_IO:1|datatri3~1~3'
-- Equation name is '_LC1_E4', type is buried
_LC1_E4 = LCELL( _EQ008);
_EQ008 = _LC2_E8 & sw_bus
# _LC2_E8 & _LC7_E4;
-- Node name is '|LPM_RAM_IO:1|:77' from file "lpm_ram_io.tdf" line 187, column 27
-- Equation name is '_LC1_E8', type is buried
_LC1_E8 = LCELL( _EQ009);
_EQ009 = a9 & we/rd;
-- Node name is '|LPM_RAM_IO:3|datatri0~1~3~2'
-- Equation name is '_LC2_B3', type is buried
-- synthesized logic cell
_LC2_B3 = LCELL( _EQ010);
_EQ010 = we/rd
# !a9
# _EC3_B & _EC4_B;
-- Node name is '|LPM_RAM_IO:3|datatri0~1~3'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ011);
_EQ011 = _LC2_B3 & sw_bus
# _LC2_B3 & _LC7_B3;
-- Node name is '|LPM_RAM_IO:3|datatri1~1~3~2'
-- Equation name is '_LC3_B3', type is buried
-- synthesized logic cell
_LC3_B3 = LCELL( _EQ012);
_EQ012 = we/rd
# !a9
# _EC1_B & _EC2_B;
-- Node name is '|LPM_RAM_IO:3|datatri1~1~3'
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ013);
_EQ013 = _LC3_B3 & sw_bus
# _LC3_B3 & _LC8_B3;
-- Node name is '|LPM_RAM_IO:3|datatri2~1~3~2'
-- Equation name is '_LC5_F7', type is buried
-- synthesized logic cell
_LC5_F7 = LCELL( _EQ014);
_EQ014 = we/rd
# !a9
# _EC3_F & _EC4_A;
-- Node name is '|LPM_RAM_IO:3|datatri2~1~3'
-- Equation name is '_LC2_F7', type is buried
_LC2_F7 = LCELL( _EQ015);
_EQ015 = _LC5_F7 & sw_bus
# _LC5_F7 & _LC7_F7;
-- Node name is '|LPM_RAM_IO:3|datatri3~1~2'
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ016);
_EQ016 = !sw_bus
# a9 & !we/rd;
-- Node name is '|LPM_RAM_IO:3|datatri3~1~3~2'
-- Equation name is '_LC6_F7', type is buried
-- synthesized logic cell
_LC6_F7 = LCELL( _EQ017);
_EQ017 = we/rd
# !a9
# _EC1_A & _EC4_F;
-- Node name is '|LPM_RAM_IO:3|datatri3~1~3'
-- Equation name is '_LC1_F7', type is buried
_LC1_F7 = LCELL( _EQ018);
_EQ018 = _LC6_F7 & sw_bus
# _LC6_F7 & _LC8_F7;
-- Node name is '|wy_cdu16:10|74161:6|f74161:sub|:9' = '|wy_cdu16:10|74161:6|f74161:sub|QA'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ019, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ019 = !en_ind & _LC7_B3
# en_ind & !_LC7_B3;
-- Node name is '|wy_cdu16:10|74161:6|f74161:sub|:87' = '|wy_cdu16:10|74161:6|f74161:sub|QB'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _EQ020, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ020 = !_LC7_B3 & _LC8_B3
# !en_ind & _LC8_B3
# en_ind & _LC7_B3 & !_LC8_B3;
-- Node name is '|wy_cdu16:10|74161:6|f74161:sub|:99' = '|wy_cdu16:10|74161:6|f74161:sub|QC'
-- Equation name is '_LC7_F7', type is buried
_LC7_F7 = DFFE( _EQ021, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ021 = !_LC6_B3 & _LC7_F7
# _LC6_B3 & !_LC7_F7;
-- Node name is '|wy_cdu16:10|74161:6|f74161:sub|:110' = '|wy_cdu16:10|74161:6|f74161:sub|QD'
-- Equation name is '_LC8_F7', type is buried
_LC8_F7 = DFFE( _EQ022, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ022 = !_LC7_F7 & _LC8_F7
# !_LC6_B3 & _LC8_F7
# _LC6_B3 & _LC7_F7 & !_LC8_F7;
-- Node name is '|wy_cdu16:10|74161:6|f74161:sub|:84'
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ023);
_EQ023 = en_ind & _LC7_B3 & _LC8_B3;
-- Node name is '|wy_cdu16:16|74161:6|f74161:sub|:9' = '|wy_cdu16:16|74161:6|f74161:sub|QA'
-- Equation name is '_LC4_F7', type is buried
_LC4_F7 = DFFE( _EQ024, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ024 = _LC4_F7 & !_LC7_F7
# _LC4_F7 & !_LC6_B3
# _LC4_F7 & !_LC8_F7
# !_LC4_F7 & _LC6_B3 & _LC7_F7 & _LC8_F7;
-- Node name is '|wy_cdu16:16|74161:6|f74161:sub|:87' = '|wy_cdu16:16|74161:6|f74161:sub|QB'
-- Equation name is '_LC5_E4', type is buried
_LC5_E4 = DFFE( _EQ025, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ025 = !_LC3_F7 & _LC5_E4
# _LC3_F7 & !_LC5_E4;
-- Node name is '|wy_cdu16:16|74161:6|f74161:sub|:99' = '|wy_cdu16:16|74161:6|f74161:sub|QC'
-- Equation name is '_LC6_E4', type is buried
_LC6_E4 = DFFE( _EQ026, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ026 = !_LC5_E4 & _LC6_E4
# !_LC3_F7 & _LC6_E4
# _LC3_F7 & _LC5_E4 & !_LC6_E4;
-- Node name is '|wy_cdu16:16|74161:6|f74161:sub|:110' = '|wy_cdu16:16|74161:6|f74161:sub|QD'
-- Equation name is '_LC7_E4', type is buried
_LC7_E4 = DFFE( _EQ027, GLOBAL( we_clk), GLOBAL( ind_clr), VCC, VCC);
_EQ027 = !_LC5_E4 & _LC7_E4
# !_LC3_F7 & _LC7_E4
# !_LC6_E4 & _LC7_E4
# _LC3_F7 & _LC5_E4 & _LC6_E4 & !_LC7_E4;
-- Node name is '|wy_cdu16:16|74161:6|f74161:sub|:80'
-- Equation name is '_LC3_F7', type is buried
_LC3_F7 = LCELL( _EQ028);
_EQ028 = _LC4_F7 & _LC6_B3 & _LC7_F7 & _LC8_F7;
-- Node name is '|LPM_RAM_IO:1|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_F', type is memory
_EC1_F = MEMORY_SEGMENT( dio4, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:1|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_A', type is memory
_EC2_A = MEMORY_SEGMENT( dio5, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:1|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_E', type is memory
_EC3_E = MEMORY_SEGMENT( dio6, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:1|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_E', type is memory
_EC1_E = MEMORY_SEGMENT( dio7, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:2|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_B', type is memory
_EC4_B = MEMORY_SEGMENT( dio0, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:2|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_B', type is memory
_EC2_B = MEMORY_SEGMENT( dio1, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:2|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_F', type is memory
_EC3_F = MEMORY_SEGMENT( dio2, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:2|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_F', type is memory
_EC4_F = MEMORY_SEGMENT( dio3, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:3|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_B', type is memory
_EC3_B = MEMORY_SEGMENT( dio0, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:3|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_B', type is memory
_EC1_B = MEMORY_SEGMENT( dio1, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:3|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_A', type is memory
_EC4_A = MEMORY_SEGMENT( dio2, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:3|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC1_A', type is memory
_EC1_A = MEMORY_SEGMENT( dio3, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_0' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_F', type is memory
_EC2_F = MEMORY_SEGMENT( dio4, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_1' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC3_A', type is memory
_EC3_A = MEMORY_SEGMENT( dio5, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_2' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC4_E', type is memory
_EC4_E = MEMORY_SEGMENT( dio6, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
-- Node name is '|LPM_RAM_IO:4|altram:sram|segment0_3' from file "altram.tdf" line 98, column 12
-- Equation name is '_EC2_E', type is memory
_EC2_E = MEMORY_SEGMENT( dio7, GLOBAL( we_clk), VCC, _LC1_E8, VCC, a0, a1, a2, a3, a4, a5, a6, a7, a8, VCC, VCC,);
Project Information e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,907K
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