📄 wycunchuqibujian.rpt
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Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
118 - - - 06 INPUT 0 0 0 16 a0
64 - - - 09 INPUT 0 0 0 16 a1
114 - - - 04 INPUT 0 0 0 16 a2
72 - - - 03 INPUT 0 0 0 16 a3
119 - - - 07 INPUT 0 0 0 16 a4
112 - - - 02 INPUT 0 0 0 16 a5
121 - - - 10 INPUT 0 0 0 16 a6
125 - - - -- INPUT 0 0 0 16 a7
126 - - - -- INPUT 0 0 0 16 a8
56 - - - -- INPUT 0 0 0 10 a9
9 - - B -- BIDIR 0 1 0 2 dio0
10 - - B -- BIDIR 0 1 0 2 dio1
80 - - F -- BIDIR 0 1 0 2 dio2
81 - - F -- BIDIR 0 1 0 2 dio3
31 - - F -- BIDIR 0 1 0 2 dio4
102 - - A -- BIDIR 0 1 0 2 dio5
26 - - E -- BIDIR 0 1 0 2 dio6
87 - - E -- BIDIR 0 1 0 2 dio7
97 - - B -- INPUT 0 0 0 3 en_ind
54 - - - -- INPUT G 0 0 0 0 ind_clr
73 - - - 01 INPUT 0 0 0 9 sw_bus
55 - - - -- INPUT G 0 0 0 0 we_clk
124 - - - -- INPUT 0 0 0 10 we/rd
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - B -- TRI 0 1 0 2 dio0
10 - - B -- TRI 0 1 0 2 dio1
80 - - F -- TRI 0 1 0 2 dio2
81 - - F -- TRI 0 1 0 2 dio3
31 - - F -- TRI 0 1 0 2 dio4
102 - - A -- TRI 0 1 0 2 dio5
26 - - E -- TRI 0 1 0 2 dio6
87 - - E -- TRI 0 1 0 2 dio7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 1 F -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:1|altram:sram|segment0_0
- - 2 A -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:1|altram:sram|segment0_1
- - 3 E -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:1|altram:sram|segment0_2
- - 1 E -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:1|altram:sram|segment0_3
- 1 - F 02 OR2 s 2 2 0 1 |LPM_RAM_IO:1|datatri0~1~3~2
- 2 - F 02 OR2 1 2 1 0 |LPM_RAM_IO:1|datatri0~1~3
- 3 - E 04 OR2 s 2 2 0 1 |LPM_RAM_IO:1|datatri1~1~3~2
- 2 - E 04 OR2 1 2 1 0 |LPM_RAM_IO:1|datatri1~1~3
- 3 - E 08 OR2 s 2 2 0 1 |LPM_RAM_IO:1|datatri2~1~3~2
- 4 - E 04 OR2 1 2 1 0 |LPM_RAM_IO:1|datatri2~1~3
- 2 - E 08 OR2 s 2 2 0 1 |LPM_RAM_IO:1|datatri3~1~3~2
- 1 - E 04 OR2 1 2 1 0 |LPM_RAM_IO:1|datatri3~1~3
- 1 - E 08 AND2 2 0 0 16 |LPM_RAM_IO:1|:77
- - 4 B -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:2|altram:sram|segment0_0
- - 2 B -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:2|altram:sram|segment0_1
- - 3 F -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:2|altram:sram|segment0_2
- - 4 F -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:2|altram:sram|segment0_3
- - 3 B -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:3|altram:sram|segment0_0
- - 1 B -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:3|altram:sram|segment0_1
- - 4 A -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:3|altram:sram|segment0_2
- - 1 A -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:3|altram:sram|segment0_3
- 2 - B 03 OR2 s 2 2 0 1 |LPM_RAM_IO:3|datatri0~1~3~2
- 4 - B 03 OR2 1 2 1 0 |LPM_RAM_IO:3|datatri0~1~3
- 3 - B 03 OR2 s 2 2 0 1 |LPM_RAM_IO:3|datatri1~1~3~2
- 5 - B 03 OR2 1 2 1 0 |LPM_RAM_IO:3|datatri1~1~3
- 5 - F 07 OR2 s 2 2 0 1 |LPM_RAM_IO:3|datatri2~1~3~2
- 2 - F 07 OR2 1 2 1 0 |LPM_RAM_IO:3|datatri2~1~3
- 1 - B 03 OR2 3 0 0 0 |LPM_RAM_IO:3|datatri3~1~2
- 6 - F 07 OR2 s 2 2 0 1 |LPM_RAM_IO:3|datatri3~1~3~2
- 1 - F 07 OR2 1 2 1 0 |LPM_RAM_IO:3|datatri3~1~3
- - 2 F -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:4|altram:sram|segment0_0
- - 3 A -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:4|altram:sram|segment0_1
- - 4 E -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:4|altram:sram|segment0_2
- - 2 E -- MEM_SGMT 9 2 0 1 |LPM_RAM_IO:4|altram:sram|segment0_3
- 7 - B 03 DFFE + 1 0 0 3 |wy_cdu16:10|74161:6|f74161:sub|QA (|wy_cdu16:10|74161:6|f74161:sub|:9)
- 6 - B 03 AND2 1 2 0 4 |wy_cdu16:10|74161:6|f74161:sub|:84
- 8 - B 03 DFFE + 1 1 0 2 |wy_cdu16:10|74161:6|f74161:sub|QB (|wy_cdu16:10|74161:6|f74161:sub|:87)
- 7 - F 07 DFFE + 0 1 0 4 |wy_cdu16:10|74161:6|f74161:sub|QC (|wy_cdu16:10|74161:6|f74161:sub|:99)
- 8 - F 07 DFFE + 0 2 0 3 |wy_cdu16:10|74161:6|f74161:sub|QD (|wy_cdu16:10|74161:6|f74161:sub|:110)
- 4 - F 07 DFFE + 0 3 0 2 |wy_cdu16:16|74161:6|f74161:sub|QA (|wy_cdu16:16|74161:6|f74161:sub|:9)
- 3 - F 07 AND2 0 4 0 3 |wy_cdu16:16|74161:6|f74161:sub|:80
- 5 - E 04 DFFE + 0 1 0 3 |wy_cdu16:16|74161:6|f74161:sub|QB (|wy_cdu16:16|74161:6|f74161:sub|:87)
- 6 - E 04 DFFE + 0 2 0 2 |wy_cdu16:16|74161:6|f74161:sub|QC (|wy_cdu16:16|74161:6|f74161:sub|:99)
- 7 - E 04 DFFE + 0 3 0 1 |wy_cdu16:16|74161:6|f74161:sub|QD (|wy_cdu16:16|74161:6|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 1/16( 6%)
B: 12/ 96( 12%) 7/ 48( 14%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 2/16( 12%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 11/ 96( 11%) 11/ 48( 22%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 2/16( 12%)
F: 14/ 96( 14%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 3/16( 18%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 24 we_clk
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 ind_clr
Device-Specific Information: e:\program\edamaxplus\exm8\wycunchuqibujian.rpt
wycunchuqibujian
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
a8 : INPUT;
a9 : INPUT;
en_ind : INPUT;
ind_clr : INPUT;
sw_bus : INPUT;
we_clk : INPUT;
we/rd : INPUT;
-- Node name is 'dio0'
-- Equation name is 'dio0', type is bidir
dio0 = TRI(_LC4_B3, _LC1_B3);
-- Node name is 'dio1'
-- Equation name is 'dio1', type is bidir
dio1 = TRI(_LC5_B3, _LC1_B3);
-- Node name is 'dio2'
-- Equation name is 'dio2', type is bidir
dio2 = TRI(_LC2_F7, _LC1_B3);
-- Node name is 'dio3'
-- Equation name is 'dio3', type is bidir
dio3 = TRI(_LC1_F7, _LC1_B3);
-- Node name is 'dio4'
-- Equation name is 'dio4', type is bidir
dio4 = TRI(_LC2_F2, _LC1_B3);
-- Node name is 'dio5'
-- Equation name is 'dio5', type is bidir
dio5 = TRI(_LC2_E4, _LC1_B3);
-- Node name is 'dio6'
-- Equation name is 'dio6', type is bidir
dio6 = TRI(_LC4_E4, _LC1_B3);
-- Node name is 'dio7'
-- Equation name is 'dio7', type is bidir
dio7 = TRI(_LC1_E4, _LC1_B3);
-- Node name is '|LPM_RAM_IO:1|datatri0~1~3~2'
-- Equation name is '_LC1_F2', type is buried
-- synthesized logic cell
_LC1_F2 = LCELL( _EQ001);
_EQ001 = we/rd
# !a9
# _EC1_F & _EC2_F;
-- Node name is '|LPM_RAM_IO:1|datatri0~1~3'
-- Equation name is '_LC2_F2', type is buried
_LC2_F2 = LCELL( _EQ002);
_EQ002 = _LC1_F2 & sw_bus
# _LC1_F2 & _LC4_F7;
-- Node name is '|LPM_RAM_IO:1|datatri1~1~3~2'
-- Equation name is '_LC3_E4', type is buried
-- synthesized logic cell
_LC3_E4 = LCELL( _EQ003);
_EQ003 = we/rd
# !a9
# _EC2_A & _EC3_A;
-- Node name is '|LPM_RAM_IO:1|datatri1~1~3'
-- Equation name is '_LC2_E4', type is buried
_LC2_E4 = LCELL( _EQ004);
_EQ004 = _LC3_E4 & sw_bus
# _LC3_E4 & _LC5_E4;
-- Node name is '|LPM_RAM_IO:1|datatri2~1~3~2'
-- Equation name is '_LC3_E8', type is buried
-- synthesized logic cell
_LC3_E8 = LCELL( _EQ005);
_EQ005 = we/rd
# !a9
# _EC3_E & _EC4_E;
-- Node name is '|LPM_RAM_IO:1|datatri2~1~3'
-- Equation name is '_LC4_E4', type is buried
_LC4_E4 = LCELL( _EQ006);
_EQ006 = _LC3_E8 & sw_bus
# _LC3_E8 & _LC6_E4;
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