📄 wybed_7seg.rpt
字号:
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\edamaxplus\exm9\wybed_7seg.rpt
wybed_7seg
** EQUATIONS **
q0 : INPUT;
q1 : INPUT;
q2 : INPUT;
q3 : INPUT;
-- Node name is 'a' from file "wybed_7seg.tdf" line 6, column 16
-- Equation name is 'a', type is output
a = _LC1_B3;
-- Node name is 'b' from file "wybed_7seg.tdf" line 6, column 18
-- Equation name is 'b', type is output
b = _LC2_B3;
-- Node name is 'c' from file "wybed_7seg.tdf" line 6, column 20
-- Equation name is 'c', type is output
c = _LC4_B3;
-- Node name is 'd' from file "wybed_7seg.tdf" line 6, column 22
-- Equation name is 'd', type is output
d = _LC7_A24;
-- Node name is 'e' from file "wybed_7seg.tdf" line 6, column 24
-- Equation name is 'e', type is output
e = _LC1_A24;
-- Node name is 'f' from file "wybed_7seg.tdf" line 6, column 26
-- Equation name is 'f', type is output
f = _LC8_B3;
-- Node name is 'g' from file "wybed_7seg.tdf" line 6, column 28
-- Equation name is 'g', type is output
g = _LC8_A24;
-- Node name is ':44' from file "wybed_7seg.tdf" line 7, column 8
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = LCELL( _EQ001);
_EQ001 = !q0 & !q1 & !q2 & !q3;
-- Node name is ':116' from file "wybed_7seg.tdf" line 15, column 8
-- Equation name is '_LC5_A24', type is buried
_LC5_A24 = LCELL( _EQ002);
_EQ002 = !q0 & !q1 & !q2 & q3;
-- Node name is ':139' from file "wybed_7seg.tdf" line 17, column 8
-- Equation name is '_LC4_A24', type is buried
_LC4_A24 = LCELL( _EQ003);
_EQ003 = !q0 & q1 & !q2 & q3;
-- Node name is '~168~1' from file "wybed_7seg.tdf" line 20, column 18
-- Equation name is '~168~1', location is LC5_B3, type is buried.
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ004);
_EQ004 = q0 & q1 & q2 & !q3
# q0 & !q1 & !q2 & !q3;
-- Node name is ':168' from file "wybed_7seg.tdf" line 20, column 18
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ005);
_EQ005 = q0 & q1 & !q3
# !q2 & !q3
# q0 & !q1 & q3
# !q0 & !q2
# !q1 & !q2
# !q0 & !q1 & !q3;
-- Node name is '~169~1' from file "wybed_7seg.tdf" line 20, column 20
-- Equation name is '~169~1', location is LC7_B3, type is buried.
-- synthesized logic cell
_LC7_B3 = LCELL( _EQ006);
_EQ006 = !q2 & q3
# !q1 & q2 & !q3
# !q0 & q2 & !q3;
-- Node name is ':169' from file "wybed_7seg.tdf" line 20, column 20
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ007);
_EQ007 = _LC3_B3
# _LC5_B3
# _LC6_B3
# _LC7_B3;
-- Node name is ':178' from file "wybed_7seg.tdf" line 21, column 22
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = LCELL( _EQ008);
_EQ008 = !q1 & !q2 & q3
# q0 & q1 & !q2
# !q0 & !q1 & !q2
# q1 & !q2 & !q3
# !q0 & !q1 & q3
# !q0 & q2 & q3
# !q0 & q1 & !q3
# q0 & !q1 & q2;
-- Node name is ':184' from file "wybed_7seg.tdf" line 22, column 8
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = LCELL( _EQ009);
_EQ009 = q0 & q1 & q2 & q3;
-- Node name is ':185' from file "wybed_7seg.tdf" line 22, column 16
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ010);
_EQ010 = q0 & q2 & !q3
# !q0 & q3
# q1 & !q3
# !q0 & !q2
# !q1 & !q2 & q3
# q0 & q1 & q2;
-- Node name is '~186~1' from file "wybed_7seg.tdf" line 22, column 24
-- Equation name is '~186~1', location is LC3_A24, type is buried.
-- synthesized logic cell
_LC3_A24 = LCELL( _EQ011);
_EQ011 = q0 & q1 & !q2 & q3
# !q0 & !q2 & !q3
# !q0 & q2 & q3
# !q0 & q1 & !q3
# !q1 & q2 & q3;
-- Node name is ':186' from file "wybed_7seg.tdf" line 22, column 24
-- Equation name is '_LC1_A24', type is buried
_LC1_A24 = LCELL( _EQ012);
_EQ012 = _LC2_A24
# _LC3_A24
# _LC4_A24
# _LC5_A24;
-- Node name is ':187' from file "wybed_7seg.tdf" line 22, column 26
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ013);
_EQ013 = !q0 & q3
# q1 & q3
# !q2 & q3
# !q0 & !q1
# !q1 & q2 & !q3
# !q0 & q2;
-- Node name is '~188~1' from file "wybed_7seg.tdf" line 22, column 28
-- Equation name is '~188~1', location is LC6_B3, type is buried.
-- synthesized logic cell
_LC6_B3 = LCELL( _EQ014);
_EQ014 = q0 & q1 & !q2 & !q3
# q0 & !q1 & q2 & q3;
-- Node name is ':188' from file "wybed_7seg.tdf" line 22, column 28
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = LCELL( _EQ015);
_EQ015 = q1 & q3
# !q2 & q3
# !q1 & q2 & !q3
# !q0 & q1
# q1 & !q2
# q0 & q3;
Project Information e:\program\edamaxplus\exm9\wybed_7seg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,668K
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