📄 cdu255.rpt
字号:
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\program\edamaxplus\exm9\cdu255.rpt
cdu255
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\program\edamaxplus\exm9\cdu255.rpt
cdu255
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr
Device-Specific Information: e:\program\edamaxplus\exm9\cdu255.rpt
cdu255
** EQUATIONS **
clk : INPUT;
clr : INPUT;
en : INPUT;
-- Node name is ':19' = 'count0'
-- Equation name is 'count0', location is LC4_B21, type is buried.
count0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = !count0 & _LC2_B16
# count0 & !en;
-- Node name is ':18' = 'count1'
-- Equation name is 'count1', location is LC7_B21, type is buried.
count1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = count0 & !count1 & _LC2_B16
# !count0 & count1 & _LC2_B16
# count1 & !en;
-- Node name is ':17' = 'count2'
-- Equation name is 'count2', location is LC2_B21, type is buried.
count2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = count2 & _LC2_B16 & !_LC8_B21
# !count2 & _LC2_B16 & _LC8_B21
# count2 & !en;
-- Node name is ':16' = 'count3'
-- Equation name is 'count3', location is LC3_B21, type is buried.
count3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = count3 & _LC2_B16 & !_LC6_B21
# !count3 & _LC2_B16 & _LC6_B21
# count3 & !en;
-- Node name is ':15' = 'count4'
-- Equation name is 'count4', location is LC5_B16, type is buried.
count4 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = count4 & _LC2_B16 & !_LC5_B21
# !count4 & _LC2_B16 & _LC5_B21
# count4 & !en;
-- Node name is ':14' = 'count5'
-- Equation name is 'count5', location is LC1_B16, type is buried.
count5 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = count5 & _LC2_B16 & !_LC4_B15
# !count5 & _LC2_B16 & _LC4_B15
# count5 & !en;
-- Node name is ':13' = 'count6'
-- Equation name is 'count6', location is LC8_B16, type is buried.
count6 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = count6 & _LC2_B16 & !_LC3_B16
# !count6 & _LC2_B16 & _LC3_B16
# count6 & !en;
-- Node name is ':12' = 'count7'
-- Equation name is 'count7', location is LC7_B16, type is buried.
count7 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = count7 & _LC2_B16 & !_LC4_B16
# !count7 & _LC2_B16 & _LC4_B16
# count7 & !en;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = count0;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = count1;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = count2;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = count3;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = count4;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = count5;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = count6;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = count7;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B21', type is buried
_LC8_B21 = LCELL( _EQ009);
_EQ009 = count0 & count1;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:125' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B21', type is buried
_LC6_B21 = LCELL( _EQ010);
_EQ010 = count0 & count1 & count2;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:129' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B21', type is buried
_LC5_B21 = LCELL( _EQ011);
_EQ011 = count3 & _LC6_B21;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:133' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B15', type is buried
_LC4_B15 = LCELL( _EQ012);
_EQ012 = count4 & _LC5_B21;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:137' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ013);
_EQ013 = count5 & _LC4_B15;
-- Node name is '|LPM_ADD_SUB:132|addcore:adder|:141' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ014);
_EQ014 = count6 & _LC3_B16;
-- Node name is '~83~1'
-- Equation name is '~83~1', location is LC6_B16, type is buried.
-- synthesized logic cell
_LC6_B16 = LCELL( _EQ015);
_EQ015 = !count3
# !count4
# !count5
# !count6;
-- Node name is '~83~2'
-- Equation name is '~83~2', location is LC1_B21, type is buried.
-- synthesized logic cell
_LC1_B21 = LCELL( _EQ016);
_EQ016 = count0
# !count1
# !count2;
-- Node name is '~263~1'
-- Equation name is '~263~1', location is LC2_B16, type is buried.
-- synthesized logic cell
_LC2_B16 = LCELL( _EQ017);
_EQ017 = !count7 & en
# en & _LC6_B16
# en & _LC1_B21;
Project Information e:\program\edamaxplus\exm9\cdu255.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,763K
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