wyscan3_3.rpt

这是在max+plusII环境下编译的双端口存储器模拟实验

q4       =  _LC6_A15;

-- Node name is 'q5' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q5', type is output 
q5       =  _LC7_C9;

-- Node name is 'tt~5~2' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~2', location is LC2_A15, type is buried.
-- synthesized logic cell 
_LC2_A15 = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~3' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~3', location is LC5_C9, type is buried.
-- synthesized logic cell 
_LC5_C9  = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~4' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~4', location is LC3_C9, type is buried.
-- synthesized logic cell 
_LC3_C9  = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~5' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~5', location is LC8_A15, type is buried.
-- synthesized logic cell 
_LC8_A15 = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~6' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~6', location is LC4_A15, type is buried.
-- synthesized logic cell 
_LC4_A15 = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~7' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~7', location is LC5_A15, type is buried.
-- synthesized logic cell 
_LC5_A15 = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~8' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~8', location is LC1_C9, type is buried.
-- synthesized logic cell 
_LC1_C9  = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~9' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~9', location is LC6_A15, type is buried.
-- synthesized logic cell 
_LC6_A15 = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5~10' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5~10', location is LC7_C9, type is buried.
-- synthesized logic cell 
_LC7_C9  = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~5' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~5', location is LC6_B19, type is buried.
tt~5     = DFFE(!tt~6, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is 'tt~6' from file "wyscan3_3.tdf" line 4, column 10
-- Equation name is 'tt~6', location is LC8_B19, type is buried.
tt~6     = DFFE(!tt~5, GLOBAL( scan_clk),  VCC,  VCC,  VCC);

-- Node name is '~142~1' from file "wyscan3_3.tdf" line 24, column 14
-- Equation name is '~142~1', location is LC1_C23, type is buried.
-- synthesized logic cell 
_LC1_C23 = LCELL( _EQ001);
  _EQ001 =  ir23
         #  ir17
         #  iri23;

-- Node name is '~142~2' from file "wyscan3_3.tdf" line 24, column 14
-- Equation name is '~142~2', location is LC2_C23, type is buried.
-- synthesized logic cell 
_LC2_C23 = LCELL( _EQ002);
  _EQ002 =  bus17
         #  _LC1_C23
         #  bus23;

-- Node name is ':142' from file "wyscan3_3.tdf" line 24, column 14
-- Equation name is '_LC4_C23', type is buried 
_LC4_C23 = LCELL( _EQ003);
  _EQ003 =  _LC2_C23 &  tt~5
         #  iri17 & !tt~6;

-- Node name is '~144~1' from file "wyscan3_3.tdf" line 24, column 27
-- Equation name is '~144~1', location is LC1_A15, type is buried.
-- synthesized logic cell 
_LC1_A15 = LCELL( _EQ004);
  _EQ004 =  ir22
         #  ir16
         #  iri22;

-- Node name is '~144~2' from file "wyscan3_3.tdf" line 24, column 27
-- Equation name is '~144~2', location is LC7_A15, type is buried.
-- synthesized logic cell 
_LC7_A15 = LCELL( _EQ005);
  _EQ005 =  bus16
         #  _LC1_A15
         #  bus22;

-- Node name is ':144' from file "wyscan3_3.tdf" line 24, column 27
-- Equation name is '_LC3_A15', type is buried 
_LC3_A15 = LCELL( _EQ006);
  _EQ006 =  _LC7_A15 &  tt~5
         #  iri16 & !tt~6;

-- Node name is '~146~1' from file "wyscan3_3.tdf" line 24, column 40
-- Equation name is '~146~1', location is LC5_B19, type is buried.
-- synthesized logic cell 
_LC5_B19 = LCELL( _EQ007);
  _EQ007 =  ir21
         #  ir15
         #  iri21;

-- Node name is '~146~2' from file "wyscan3_3.tdf" line 24, column 40
-- Equation name is '~146~2', location is LC7_B19, type is buried.
-- synthesized logic cell 
_LC7_B19 = LCELL( _EQ008);
  _EQ008 =  bus15
         #  _LC5_B19
         #  bus21;

-- Node name is ':146' from file "wyscan3_3.tdf" line 24, column 40
-- Equation name is '_LC4_B19', type is buried 
_LC4_B19 = LCELL( _EQ009);
  _EQ009 =  _LC7_B19 &  tt~5
         #  iri15 & !tt~6;

-- Node name is '~148~1' from file "wyscan3_3.tdf" line 24, column 53
-- Equation name is '~148~1', location is LC1_B19, type is buried.
-- synthesized logic cell 
_LC1_B19 = LCELL( _EQ010);
  _EQ010 =  ir20
         #  ir14
         #  iri20;

-- Node name is '~148~2' from file "wyscan3_3.tdf" line 24, column 53
-- Equation name is '~148~2', location is LC2_B19, type is buried.
-- synthesized logic cell 
_LC2_B19 = LCELL( _EQ011);
  _EQ011 =  bus14
         #  _LC1_B19
         #  bus20;

-- Node name is ':148' from file "wyscan3_3.tdf" line 24, column 53
-- Equation name is '_LC3_B19', type is buried 
_LC3_B19 = LCELL( _EQ012);
  _EQ012 =  _LC2_B19 &  tt~5
         #  iri14 & !tt~6;



Project Information                   e:\program\edamaxplus\exm9\wyscan3_3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,126K