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📄 wyscan3_3.rpt

📁 这是在max+plusII环境下编译的双端口存储器模拟实验
💻 RPT
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Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:          e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  79      -     -    -    24     OUTPUT                0    0    0    0  bus_gw
  53      -     -    -    20     OUTPUT                0    1    0    0  bus_sw
  48      -     -    -    15     OUTPUT                0    1    0    0  ir_gw
  28      -     -    C    --     OUTPUT                0    1    0    0  iri_gw
  49      -     -    -    16     OUTPUT                0    1    0    0  iri_sw
  29      -     -    C    --     OUTPUT                0    1    0    0  ir_sw
  66      -     -    B    --     OUTPUT                0    1    0    0  out0
  23      -     -    B    --     OUTPUT                0    1    0    0  out1
  72      -     -    A    --     OUTPUT                0    1    0    0  out2
  78      -     -    -    24     OUTPUT                0    1    0    0  out3
  52      -     -    -    19     OUTPUT                0    1    0    0  q0
  71      -     -    A    --     OUTPUT                0    1    0    0  q1
  70      -     -    A    --     OUTPUT                0    1    0    0  q2
  27      -     -    C    --     OUTPUT                0    1    0    0  q3
  24      -     -    B    --     OUTPUT                0    1    0    0  q4
  30      -     -    C    --     OUTPUT                0    1    0    0  q5


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:          e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      2     -    A    15       DFFE   +s           0    1    1    0  tt~5~2
   -      5     -    C    09       DFFE   +s           0    1    1    0  tt~5~3
   -      3     -    C    09       DFFE   +s           0    1    1    0  tt~5~4
   -      8     -    A    15       DFFE   +s           0    1    1    0  tt~5~5
   -      4     -    A    15       DFFE   +s           0    1    1    0  tt~5~6
   -      5     -    A    15       DFFE   +s           0    1    1    0  tt~5~7
   -      1     -    C    09       DFFE   +s           0    1    1    0  tt~5~8
   -      6     -    A    15       DFFE   +s           0    1    1    0  tt~5~9
   -      7     -    C    09       DFFE   +s           0    1    1    0  tt~5~10
   -      6     -    B    19       DFFE   +            0    1    1    5  tt~5
   -      8     -    B    19       DFFE   +            0    1    1   14  tt~6
   -      1     -    C    23        OR2    s           3    0    0    1  ~142~1
   -      2     -    C    23        OR2    s           2    1    0    1  ~142~2
   -      4     -    C    23        OR2                1    3    1    0  :142
   -      1     -    A    15        OR2    s           3    0    0    1  ~144~1
   -      7     -    A    15        OR2    s           2    1    0    1  ~144~2
   -      3     -    A    15        OR2                1    3    1    0  :144
   -      5     -    B    19        OR2    s           3    0    0    1  ~146~1
   -      7     -    B    19        OR2    s           2    1    0    1  ~146~2
   -      4     -    B    19        OR2                1    3    1    0  :146
   -      1     -    B    19        OR2    s           3    0    0    1  ~148~1
   -      2     -    B    19        OR2    s           2    1    0    1  ~148~2
   -      3     -    B    19        OR2                1    3    1    0  :148


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:          e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       6/ 96(  6%)     0/ 48(  0%)     5/ 48( 10%)    6/16( 37%)      3/16( 18%)     0/16(  0%)
B:       8/ 96(  8%)     0/ 48(  0%)     2/ 48(  4%)    6/16( 37%)      3/16( 18%)     0/16(  0%)
C:       6/ 96(  6%)     4/ 48(  8%)     2/ 48(  4%)    5/16( 31%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      2/24(  8%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
16:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
17:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      1/24(  4%)     0/4(  0%)      2/4( 50%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:          e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       11         scan_clk


Device-Specific Information:          e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3

** EQUATIONS **

bus14    : INPUT;
bus15    : INPUT;
bus16    : INPUT;
bus17    : INPUT;
bus20    : INPUT;
bus21    : INPUT;
bus22    : INPUT;
bus23    : INPUT;
iri14    : INPUT;
iri15    : INPUT;
iri16    : INPUT;
iri17    : INPUT;
iri20    : INPUT;
iri21    : INPUT;
iri22    : INPUT;
iri23    : INPUT;
ir14     : INPUT;
ir15     : INPUT;
ir16     : INPUT;
ir17     : INPUT;
ir20     : INPUT;
ir21     : INPUT;
ir22     : INPUT;
ir23     : INPUT;
scan_clk : INPUT;

-- Node name is 'bus_gw' from file "wyscan3_3.tdf" line 24, column 72
-- Equation name is 'bus_gw', type is output 
bus_gw   =  GND;

-- Node name is 'bus_sw' from file "wyscan3_3.tdf" line 24, column 62
-- Equation name is 'bus_sw', type is output 
bus_sw   =  tt~5;

-- Node name is 'ir_gw' from file "wyscan3_3.tdf" line 18, column 67
-- Equation name is 'ir_gw', type is output 
ir_gw    =  _LC2_A15;

-- Node name is 'iri_gw' from file "wyscan3_3.tdf" line 12, column 72
-- Equation name is 'iri_gw', type is output 
iri_gw   =  _LC3_C9;

-- Node name is 'iri_sw' from file "wyscan3_3.tdf" line 12, column 62
-- Equation name is 'iri_sw', type is output 
iri_sw   =  _LC8_A15;

-- Node name is 'ir_sw' from file "wyscan3_3.tdf" line 18, column 58
-- Equation name is 'ir_sw', type is output 
ir_sw    =  _LC5_C9;

-- Node name is 'out0' from file "wyscan3_3.tdf" line 24, column 49
-- Equation name is 'out0', type is output 
out0     =  _LC3_B19;

-- Node name is 'out1' from file "wyscan3_3.tdf" line 24, column 36
-- Equation name is 'out1', type is output 
out1     =  _LC4_B19;

-- Node name is 'out2' from file "wyscan3_3.tdf" line 24, column 23
-- Equation name is 'out2', type is output 
out2     =  _LC3_A15;

-- Node name is 'out3' from file "wyscan3_3.tdf" line 24, column 10
-- Equation name is 'out3', type is output 
out3     =  _LC4_C23;

-- Node name is 'q0' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q0', type is output 
q0       = !tt~6;

-- Node name is 'q1' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q1', type is output 
q1       =  _LC4_A15;

-- Node name is 'q2' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q2', type is output 
q2       =  _LC5_A15;

-- Node name is 'q3' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q3', type is output 
q3       =  _LC1_C9;

-- Node name is 'q4' from file "wyscan3_3.tdf" line 23, column 11
-- Equation name is 'q4', type is output 

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