📄 wyscan3_3.rpt
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Project Information e:\program\edamaxplus\exm9\wyscan3_3.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/09/2008 21:55:27
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
wyscan3_3
EPF10K10LC84-3 25 16 0 0 0 % 23 3 %
User Pins: 25 16 0
Project Information e:\program\edamaxplus\exm9\wyscan3_3.rpt
** STATE MACHINE ASSIGNMENTS **
tt: MACHINE
OF BITS (
tt~6,
tt~5
)
WITH STATES (
t0 = B"00",
t1 = B"11",
t2 = B"10",
t3 = B"10",
t4 = B"10",
t5 = B"10"
);
Device-Specific Information: e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3
***** Logic for device 'wyscan3_3' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R s R R O
E E E E E E E E c E E N
S S S S S S S V S a G S S b F
E E E E E E E C E b n i N E E u _ ^
R R R R R R R C R u _ r i D R R s o # D n
V V V V V V V I V s c i r I V V _ u T O C
E E E E E E E N E 1 l 2 1 N E E g t C N E
D D D D D D D T D 4 k 0 7 T D D w 3 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | iri16
^nCE | 14 72 | out2
#TDI | 15 71 | q1
iri22 | 16 70 | q2
ir16 | 17 69 | bus22
ir22 | 18 68 | GNDINT
bus16 | 19 67 | iri14
VCCINT | 20 66 | out0
bus21 | 21 65 | ir15
ir21 | 22 EPF10K10LC84-3 64 | iri15
out1 | 23 63 | VCCINT
q4 | 24 62 | iri23
iri21 | 25 61 | ir23
GNDINT | 26 60 | iri17
q3 | 27 59 | bus23
iri_gw | 28 58 | bus17
ir_sw | 29 57 | #TMS
q5 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G i b i V G R i i b R q b
C n E E E E E C N r u r C N E r r u E 0 u
C C S S S S S C D 2 s 1 C D S _ i s S s
I O E E E E E I I 0 2 4 I I E g _ 1 E _
N N R R R R R N N 0 N N R w s 5 R s
T F V V V V V T T T T V w V w
I E E E E E E E
G D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A15 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
B19 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 12/22( 54%)
C9 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
C23 3/ 8( 37%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 35/53 ( 66%)
Total logic cells used: 23/576 ( 3%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.21/4 ( 55%)
Total fan-in: 51/2304 ( 2%)
Total input pins required: 25
Total input I/O cell registers required: 0
Total output pins required: 16
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 23
Total flipflops required: 11
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 17/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 7/0
Total: 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 8 0 0 0 8 0 0 0 3 0 23/0
Device-Specific Information: e:\program\edamaxplus\exm9\wyscan3_3.rpt
wyscan3_3
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT 0 0 0 1 bus14
50 - - - 17 INPUT 0 0 0 1 bus15
19 - - A -- INPUT 0 0 0 1 bus16
58 - - C -- INPUT 0 0 0 1 bus17
43 - - - -- INPUT 0 0 0 1 bus20
21 - - B -- INPUT 0 0 0 1 bus21
69 - - A -- INPUT 0 0 0 1 bus22
59 - - C -- INPUT 0 0 0 1 bus23
67 - - B -- INPUT 0 0 0 1 iri14
64 - - B -- INPUT 0 0 0 1 iri15
73 - - A -- INPUT 0 0 0 1 iri16
60 - - C -- INPUT 0 0 0 1 iri17
84 - - - -- INPUT 0 0 0 1 iri20
25 - - B -- INPUT 0 0 0 1 iri21
16 - - A -- INPUT 0 0 0 1 iri22
62 - - C -- INPUT 0 0 0 1 iri23
44 - - - -- INPUT 0 0 0 1 ir14
65 - - B -- INPUT 0 0 0 1 ir15
17 - - A -- INPUT 0 0 0 1 ir16
83 - - - 13 INPUT 0 0 0 1 ir17
42 - - - -- INPUT 0 0 0 1 ir20
22 - - B -- INPUT 0 0 0 1 ir21
18 - - A -- INPUT 0 0 0 1 ir22
61 - - C -- INPUT 0 0 0 1 ir23
1 - - - -- INPUT G 0 0 0 0 scan_clk
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