📄 wysdk_cunchuqibujian.rpt
字号:
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 33/ 96( 34%) 18/ 48( 37%) 11/ 48( 22%) 1/16( 6%) 6/16( 37%) 2/16( 12%)
B: 1/ 96( 1%) 2/ 48( 4%) 1/ 48( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 21/ 96( 21%) 4/ 48( 8%) 14/ 48( 29%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 0/4( 0%) 2/4( 50%)
02: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
24: 4/24( 16%) 0/4( 0%) 1/4( 25%) 1/4( 25%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 17 clk_cdu
INPUT 16 scan_clk
INPUT 8 mux3
LCELL 8 :11
LCELL 8 :21
LCELL 8 :43
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clr_cdu
INPUT 8 161clrn
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** EQUATIONS **
clk_cdu : INPUT;
clr_cdu : INPUT;
en_cdu : INPUT;
ldar : INPUT;
ldir : INPUT;
mux3 : INPUT;
pc_bus : INPUT;
rd : INPUT;
scan_clk : INPUT;
sw_bus : INPUT;
write : INPUT;
161clrn : INPUT;
161cp : INPUT;
161ld : INPUT;
-- Node name is 'ad_ir0'
-- Equation name is 'ad_ir0', type is output
ad_ir0 = _LC1_C19;
-- Node name is 'ad_ir1'
-- Equation name is 'ad_ir1', type is output
ad_ir1 = _LC1_A11;
-- Node name is 'ad_ir2'
-- Equation name is 'ad_ir2', type is output
ad_ir2 = _LC7_C1;
-- Node name is 'ad_ir3'
-- Equation name is 'ad_ir3', type is output
ad_ir3 = _LC1_C23;
-- Node name is 'ad_ir4'
-- Equation name is 'ad_ir4', type is output
ad_ir4 = _LC5_C19;
-- Node name is 'ad_ir5'
-- Equation name is 'ad_ir5', type is output
ad_ir5 = _LC5_C11;
-- Node name is 'ad_ir6'
-- Equation name is 'ad_ir6', type is output
ad_ir6 = _LC2_C2;
-- Node name is 'ad_ir7'
-- Equation name is 'ad_ir7', type is output
ad_ir7 = _LC4_C23;
-- Node name is 'adr0'
-- Equation name is 'adr0', type is output
adr0 = _LC8_A4;
-- Node name is 'adr1'
-- Equation name is 'adr1', type is output
adr1 = _LC7_A4;
-- Node name is 'adr2'
-- Equation name is 'adr2', type is output
adr2 = _LC5_A8;
-- Node name is 'adr3'
-- Equation name is 'adr3', type is output
adr3 = _LC2_A8;
-- Node name is 'adr4'
-- Equation name is 'adr4', type is output
adr4 = _LC3_A23;
-- Node name is 'adr5'
-- Equation name is 'adr5', type is output
adr5 = _LC4_A23;
-- Node name is 'adr6'
-- Equation name is 'adr6', type is output
adr6 = _LC1_A8;
-- Node name is 'adr7'
-- Equation name is 'adr7', type is output
adr7 = _LC3_A8;
-- Node name is 'bus_gw'
-- Equation name is 'bus_gw', type is output
bus_gw = GND;
-- Node name is 'bus_sw'
-- Equation name is 'bus_sw', type is output
bus_sw = _LC2_C22;
-- Node name is 'bus0'
-- Equation name is 'bus0', type is bidir
bus0 = TRI(_LC2_A1, _LC1_A1);
-- Node name is 'bus1'
-- Equation name is 'bus1', type is bidir
bus1 = TRI(_LC3_A1, _LC1_A1);
-- Node name is 'bus2'
-- Equation name is 'bus2', type is bidir
bus2 = TRI(_LC4_A1, _LC1_A1);
-- Node name is 'bus3'
-- Equation name is 'bus3', type is bidir
bus3 = TRI(_LC1_A23, _LC1_A1);
-- Node name is 'bus4'
-- Equation name is 'bus4', type is bidir
bus4 = TRI(_LC8_A23, _LC1_A1);
-- Node name is 'bus5'
-- Equation name is 'bus5', type is bidir
bus5 = TRI(_LC5_A23, _LC1_A1);
-- Node name is 'bus6'
-- Equation name is 'bus6', type is bidir
bus6 = TRI(_LC6_A8, _LC1_A1);
-- Node name is 'bus7'
-- Equation name is 'bus7', type is bidir
bus7 = TRI(_LC8_A8, _LC1_A1);
-- Node name is 'ir_gw'
-- Equation name is 'ir_gw', type is output
ir_gw = _LC6_C22;
-- Node name is 'iri_gw'
-- Equation name is 'iri_gw', type is output
iri_gw = _LC1_C22;
-- Node name is 'iri_sw'
-- Equation name is 'iri_sw', type is output
iri_sw = _LC1_C17;
-- Node name is 'ir_sw'
-- Equation name is 'ir_sw', type is output
ir_sw = _LC8_C22;
-- Node name is 'seg_a'
-- Equation name is 'seg_a', type is output
seg_a = _LC6_C13;
-- Node name is 'seg_b'
-- Equation name is 'seg_b', type is output
seg_b = _LC1_C24;
-- Node name is 'seg_c'
-- Equation name is 'seg_c', type is output
seg_c = _LC5_C13;
-- Node name is 'seg_d'
-- Equation name is 'seg_d', type is output
seg_d = _LC6_C24;
-- Node name is 'seg_e'
-- Equation name is 'seg_e', type is output
seg_e = _LC1_C13;
-- Node name is 'seg_f'
-- Equation name is 'seg_f', type is output
seg_f = _LC4_C16;
-- Node name is 'seg_g'
-- Equation name is 'seg_g', type is output
seg_g = _LC3_C24;
-- Node name is '|CDU255:63|:19' = '|CDU255:63|count0'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = DFFE( _EQ001, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ001 = _LC1_A15 & !_LC2_A21
# !en_cdu & _LC2_A21;
-- Node name is '|CDU255:63|:18' = '|CDU255:63|count1'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = DFFE( _EQ002, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ002 = _LC1_A15 & !_LC2_A21 & _LC3_A15
# _LC1_A15 & _LC2_A21 & !_LC3_A15
# !en_cdu & _LC3_A15;
-- Node name is '|CDU255:63|:17' = '|CDU255:63|count2'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = DFFE( _EQ003, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ003 = _LC1_A15 & !_LC5_A15 & _LC6_A15
# _LC1_A15 & _LC5_A15 & !_LC6_A15
# !en_cdu & _LC6_A15;
-- Node name is '|CDU255:63|:16' = '|CDU255:63|count3'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _EQ004, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ004 = _LC1_A15 & !_LC7_A15 & _LC8_A15
# _LC1_A15 & _LC7_A15 & !_LC8_A15
# !en_cdu & _LC8_A15;
-- Node name is '|CDU255:63|:15' = '|CDU255:63|count4'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = DFFE( _EQ005, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ005 = _LC1_A15 & !_LC2_A15 & _LC5_A18
# _LC1_A15 & _LC2_A15 & !_LC5_A18
# !en_cdu & _LC5_A18;
-- Node name is '|CDU255:63|:14' = '|CDU255:63|count5'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = DFFE( _EQ006, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ006 = _LC1_A15 & _LC4_A18 & !_LC6_A18
# _LC1_A15 & !_LC4_A18 & _LC6_A18
# !en_cdu & _LC4_A18;
-- Node name is '|CDU255:63|:13' = '|CDU255:63|count6'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = DFFE( _EQ007, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ007 = _LC1_A15 & _LC3_A18 & !_LC7_A18
# _LC1_A15 & !_LC3_A18 & _LC7_A18
# !en_cdu & _LC3_A18;
-- Node name is '|CDU255:63|:12' = '|CDU255:63|count7'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ008, GLOBAL( clk_cdu), GLOBAL(!clr_cdu), VCC, VCC);
_EQ008 = _LC1_A15 & _LC1_A18 & !_LC8_A18
# _LC1_A15 & !_LC1_A18 & _LC8_A18
# !en_cdu & _LC1_A18;
-- Node name is '|CDU255:63|LPM_ADD_SUB:132|addcore:adder|:121' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = LCELL( _EQ009);
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