📄 wysdk_cunchuqibujian.rpt
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Total input pins required: 14
Total input I/O cell registers required: 0
Total output pins required: 29
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 8
Total reserved pins required 0
Total logic cells required: 111
Total flipflops required: 46
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 30/ 576 ( 5%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 1 0 8 0 0 0 8 8 0 1 0 8 0 0 8 1 0 8 0 0 1 0 8 0 60/8
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 1 1 0 0 0 0 0 0 0 0 1 0 8 8 0 0 1 8 0 8 0 0 8 7 8 51/8
Total: 9 2 0 8 0 0 0 8 8 0 2 0 16 8 0 8 2 8 8 8 0 1 8 15 8 111/16
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
9 - - - 02 BIDIR 0 1 0 4 bus0
11 - - - 01 BIDIR 0 1 0 4 bus1
10 - - - 01 BIDIR 0 1 0 4 bus2
80 - - - 23 BIDIR 0 1 0 4 bus3
78 - - - 24 BIDIR 0 1 0 4 bus4
70 - - A -- BIDIR 0 1 0 4 bus5
36 - - - 07 BIDIR 0 1 0 4 bus6
69 - - A -- BIDIR 0 1 0 4 bus7
1 - - - -- INPUT G 0 0 0 1 clk_cdu
2 - - - -- INPUT G 0 0 0 0 clr_cdu
84 - - - -- INPUT 0 0 0 9 en_cdu
49 - - - 16 INPUT 0 0 0 1 ldar
51 - - - 18 INPUT 0 0 0 1 ldir
44 - - - -- INPUT G 0 0 0 0 mux3
50 - - - 17 INPUT 0 0 0 9 pc_bus
3 - - - 12 INPUT 0 0 0 10 rd
43 - - - -- INPUT G 0 0 0 2 scan_clk
16 - - A -- INPUT 0 0 0 9 sw_bus
35 - - - 06 INPUT 0 0 0 1 write
42 - - - -- INPUT G 0 0 0 0 161clrn
7 - - - 03 INPUT 0 0 0 1 161cp
37 - - - 09 INPUT 0 0 0 8 161ld
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
52 - - - 19 OUTPUT 0 1 0 0 ad_ir0
39 - - - 11 OUTPUT 0 1 0 0 ad_ir1
30 - - C -- OUTPUT 0 1 0 0 ad_ir2
62 - - C -- OUTPUT 0 1 0 0 ad_ir3
53 - - - 20 OUTPUT 0 1 0 0 ad_ir4
29 - - C -- OUTPUT 0 1 0 0 ad_ir5
28 - - C -- OUTPUT 0 1 0 0 ad_ir6
60 - - C -- OUTPUT 0 1 0 0 ad_ir7
18 - - A -- OUTPUT 0 1 0 0 adr0
19 - - A -- OUTPUT 0 1 0 0 adr1
65 - - B -- OUTPUT 0 1 0 0 adr2
17 - - A -- OUTPUT 0 1 0 0 adr3
72 - - A -- OUTPUT 0 1 0 0 adr4
71 - - A -- OUTPUT 0 1 0 0 adr5
22 - - B -- OUTPUT 0 1 0 0 adr6
23 - - B -- OUTPUT 0 1 0 0 adr7
25 - - B -- OUTPUT 0 0 0 0 bus_gw
61 - - C -- OUTPUT 0 1 0 0 bus_sw
9 - - - 02 TRI 0 1 0 4 bus0
11 - - - 01 TRI 0 1 0 4 bus1
10 - - - 01 TRI 0 1 0 4 bus2
80 - - - 23 TRI 0 1 0 4 bus3
78 - - - 24 TRI 0 1 0 4 bus4
70 - - A -- TRI 0 1 0 4 bus5
36 - - - 07 TRI 0 1 0 4 bus6
69 - - A -- TRI 0 1 0 4 bus7
64 - - B -- OUTPUT 0 1 0 0 ir_gw
81 - - - 22 OUTPUT 0 1 0 0 iri_gw
27 - - C -- OUTPUT 0 1 0 0 iri_sw
54 - - - 21 OUTPUT 0 1 0 0 ir_sw
47 - - - 14 OUTPUT 0 1 0 0 seg_a
73 - - A -- OUTPUT 0 1 0 0 seg_b
59 - - C -- OUTPUT 0 1 0 0 seg_c
58 - - C -- OUTPUT 0 1 0 0 seg_d
83 - - - 13 OUTPUT 0 1 0 0 seg_e
48 - - - 15 OUTPUT 0 1 0 0 seg_f
79 - - - 24 OUTPUT 0 1 0 0 seg_g
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 15 AND2 0 2 0 1 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:121
- 7 - A 15 AND2 0 3 0 1 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:125
- 2 - A 15 AND2 0 4 0 4 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:129
- 6 - A 18 AND2 0 2 0 1 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:133
- 7 - A 18 AND2 0 3 0 1 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:137
- 8 - A 18 AND2 0 4 0 1 |CDU255:63|LPM_ADD_SUB:132|addcore:adder|:141
- 1 - A 18 DFFE + 1 2 0 2 |CDU255:63|count7 (|CDU255:63|:12)
- 3 - A 18 DFFE + 1 2 0 3 |CDU255:63|count6 (|CDU255:63|:13)
- 4 - A 18 DFFE + 1 2 0 4 |CDU255:63|count5 (|CDU255:63|:14)
- 5 - A 18 DFFE + 1 2 0 5 |CDU255:63|count4 (|CDU255:63|:15)
- 8 - A 15 DFFE + 1 2 0 3 |CDU255:63|count3 (|CDU255:63|:16)
- 6 - A 15 DFFE + 1 2 0 4 |CDU255:63|count2 (|CDU255:63|:17)
- 3 - A 15 DFFE + 1 2 0 5 |CDU255:63|count1 (|CDU255:63|:18)
- 2 - A 21 DFFE + 1 1 0 6 |CDU255:63|count0 (|CDU255:63|:19)
- 4 - A 15 OR2 s 0 4 0 1 |CDU255:63|~83~1
- 2 - A 18 OR2 s 0 3 0 1 |CDU255:63|~83~2
- 1 - A 15 OR2 s 1 3 0 8 |CDU255:63|~221~1
- - 7 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_0
- - 8 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_1
- - 6 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_2
- - 1 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_3
- - 2 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_4
- - 5 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_5
- - 3 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_6
- - 4 A -- MEM_SGMT 0 10 0 1 |LPM_RAM_IO:33|altram:sram|segment0_7
- 5 - A 01 AND2 2 0 0 8 |LPM_RAM_IO:33|:90
- - 1 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_0
- - 7 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_1
- - 4 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_2
- - 2 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_3
- - 8 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_4
- - 6 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_5
- - 5 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_6
- - 3 C -- MEM_SGMT 0 8 0 2 |LPM_ROM:67|altrom:srom|segment0_7
- 2 - C 13 AND2 0 4 0 2 |wybed_7seg:49|:58
- 3 - C 13 AND2 0 4 0 1 |wybed_7seg:49|:67
- 7 - C 24 AND2 s 0 2 0 1 |wybed_7seg:49|~78~1
- 4 - C 13 AND2 0 4 0 1 |wybed_7seg:49|:107
- 1 - C 24 OR2 0 4 1 0 |wybed_7seg:49|:168
- 5 - C 13 OR2 0 4 1 0 |wybed_7seg:49|:169
- 6 - C 24 OR2 0 4 1 0 |wybed_7seg:49|:178
- 6 - C 13 OR2 0 4 1 0 |wybed_7seg:49|:185
- 8 - C 13 OR2 s 0 4 0 1 |wybed_7seg:49|~186~1
- 1 - C 13 OR2 0 3 1 0 |wybed_7seg:49|:186
- 4 - C 24 OR2 s 0 4 0 2 |wybed_7seg:49|~187~1
- 7 - C 13 OR2 s 0 4 0 1 |wybed_7seg:49|~187~2
- 2 - C 24 OR2 s 0 4 0 1 |wybed_7seg:49|~187~3
- 4 - C 16 OR2 0 2 1 0 |wybed_7seg:49|:187
- 5 - C 24 OR2 s 0 4 0 2 |wybed_7seg:49|~188~1
- 8 - C 24 OR2 s 0 4 0 1 |wybed_7seg:49|~188~2
- 3 - C 24 OR2 0 2 1 0 |wybed_7seg:49|:188
- 1 - C 22 DFFE +s 0 1 1 0 |wyscan3_3:46|tt~5~2
- 8 - C 22 DFFE +s 0 1 1 0 |wyscan3_3:46|tt~5~3
- 6 - C 22 DFFE +s 0 1 1 0 |wyscan3_3:46|tt~5~4
- 2 - C 22 DFFE +s 0 1 1 0 |wyscan3_3:46|tt~5~5
- 1 - C 17 DFFE + 0 1 1 5 |wyscan3_3:46|tt~5
- 2 - C 17 DFFE + 0 1 0 9 |wyscan3_3:46|tt~6
- 6 - C 23 AND2 s ! 0 3 0 1 |wyscan3_3:46|~142~1
- 7 - C 23 AND2 s 0 3 0 1 |wyscan3_3:46|~142~2
- 3 - C 23 OR2 ! 0 4 0 12 |wyscan3_3:46|:142
- 5 - C 22 OR2 s ! 0 3 0 1 |wyscan3_3:46|~144~1
- 7 - C 22 OR2 s 0 3 0 1 |wyscan3_3:46|~144~2
- 3 - C 22 OR2 0 4 0 12 |wyscan3_3:46|:144
- 7 - C 17 OR2 s 0 3 0 1 |wyscan3_3:46|~146~1
- 8 - C 17 OR2 s 0 3 0 1 |wyscan3_3:46|~146~2
- 3 - C 17 OR2 0 4 0 12 |wyscan3_3:46|:146
- 7 - C 19 OR2 s 0 3 0 1 |wyscan3_3:46|~148~1
- 8 - C 19 OR2 s 0 3 0 1 |wyscan3_3:46|~148~2
- 2 - C 19 OR2 0 4 0 12 |wyscan3_3:46|:148
- 8 - A 16 AND2 2 0 0 8 :11
- 1 - A 02 AND2 2 0 0 8 :21
- 4 - C 17 AND2 2 0 0 8 :43
- 4 - A 04 DFFE 1 2 0 5 |74161:14|f74161:sub|QA (|74161:14|f74161:sub|:9)
- 6 - A 04 AND2 0 2 0 1 |74161:14|f74161:sub|:84
- 5 - A 04 DFFE 1 3 0 4 |74161:14|f74161:sub|QB (|74161:14|f74161:sub|:87)
- 3 - A 04 AND2 0 3 0 2 |74161:14|f74161:sub|:94
- 2 - A 04 DFFE 1 3 0 3 |74161:14|f74161:sub|QC (|74161:14|f74161:sub|:99)
- 4 - A 09 AND2 0 2 0 2 |74161:14|f74161:sub|:104
- 1 - A 04 DFFE 1 3 0 3 |74161:14|f74161:sub|QD (|74161:14|f74161:sub|:110)
- 3 - A 09 DFFE 1 3 0 3 |74161:15|f74161:sub|QA (|74161:15|f74161:sub|:9)
- 5 - A 09 AND2 0 2 0 2 |74161:15|f74161:sub|:80
- 6 - A 09 AND2 0 2 0 2 |74161:15|f74161:sub|:84
- 2 - A 09 DFFE 1 3 0 3 |74161:15|f74161:sub|QB (|74161:15|f74161:sub|:87)
- 7 - A 09 AND2 0 2 0 1 |74161:15|f74161:sub|:94
- 8 - A 09 DFFE 1 3 0 3 |74161:15|f74161:sub|QC (|74161:15|f74161:sub|:99)
- 1 - A 09 DFFE 1 3 0 2 |74161:15|f74161:sub|QD (|74161:15|f74161:sub|:110)
- 1 - A 01 OR2 3 0 0 0 |74244:16|~1~1~2
- 8 - A 01 OR2 s 2 2 0 1 |74244:16|~1~1~3~2
- 2 - A 01 OR2 1 2 1 0 |74244:16|~1~1~3
- 7 - A 01 OR2 s 2 2 0 1 |74244:16|~6~1~3~2
- 3 - A 01 OR2 1 2 1 0 |74244:16|~6~1~3
- 6 - A 01 OR2 s 2 2 0 1 |74244:16|~10~1~3~2
- 4 - A 01 OR2 1 2 1 0 |74244:16|~10~1~3
- 7 - A 23 OR2 s 2 2 0 1 |74244:16|~11~1~3~2
- 1 - A 23 OR2 1 2 1 0 |74244:16|~11~1~3
- 4 - A 08 OR2 s 2 2 0 1 |74244:16|~26~1~3~2
- 8 - A 08 OR2 1 2 1 0 |74244:16|~26~1~3
- 7 - A 08 OR2 s 2 2 0 1 |74244:16|~27~1~3~2
- 6 - A 08 OR2 1 2 1 0 |74244:16|~27~1~3
- 2 - A 23 OR2 s 2 2 0 1 |74244:16|~31~1~3~2
- 5 - A 23 OR2 1 2 1 0 |74244:16|~31~1~3
- 6 - A 23 OR2 s 2 2 0 1 |74244:16|~36~1~3~2
- 8 - A 23 OR2 1 2 1 0 |74244:16|~36~1~3
- 3 - A 08 DFFE 0 2 1 8 |74273:2|Q8 (|74273:2|:12)
- 1 - A 08 DFFE 0 2 1 8 |74273:2|Q7 (|74273:2|:13)
- 4 - A 23 DFFE 0 2 1 8 |74273:2|Q6 (|74273:2|:14)
- 3 - A 23 DFFE 0 2 1 8 |74273:2|Q5 (|74273:2|:15)
- 2 - A 08 DFFE 0 2 1 8 |74273:2|Q4 (|74273:2|:16)
- 5 - A 08 DFFE 0 2 1 8 |74273:2|Q3 (|74273:2|:17)
- 7 - A 04 DFFE 0 2 1 8 |74273:2|Q2 (|74273:2|:18)
- 8 - A 04 DFFE 0 2 1 8 |74273:2|Q1 (|74273:2|:19)
- 5 - C 19 DFFE + 0 1 1 8 |74298:38|QD (|74298:38|:5)
- 5 - C 11 DFFE + 0 1 1 8 |74298:38|QC (|74298:38|:6)
- 2 - C 02 DFFE + 0 1 1 8 |74298:38|QB (|74298:38|:7)
- 4 - C 23 DFFE + 0 1 1 8 |74298:38|QA (|74298:38|:8)
- 1 - C 19 DFFE + 0 1 1 8 |74298:39|QD (|74298:39|:5)
- 1 - A 11 DFFE + 0 1 1 8 |74298:39|QC (|74298:39|:6)
- 7 - C 01 DFFE + 0 1 1 8 |74298:39|QB (|74298:39|:7)
- 1 - C 23 DFFE + 0 1 1 8 |74298:39|QA (|74298:39|:8)
- 2 - C 23 DFFE 0 2 0 1 |74374:42|:13
- 4 - C 22 DFFE 0 2 0 1 |74374:42|:14
- 6 - C 17 DFFE 0 2 0 1 |74374:42|:15
- 6 - C 19 DFFE 0 2 0 1 |74374:42|:16
- 5 - C 23 DFFE 0 2 0 1 |74374:42|:17
- 3 - C 19 DFFE 0 2 0 1 |74374:42|:18
- 5 - C 17 DFFE 0 2 0 1 |74374:42|:19
- 4 - C 19 DFFE 0 2 0 1 |74374:42|:20
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\program\edamaxplus\exm9\wysdk_cunchuqibujian.rpt
wysdk_cunchuqibujian
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
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